| octeonreg.h (0fee2420) | octeonreg.h (750f12e5) |
|---|---|
| 1/* $OpenBSD: octeonreg.h,v 1.9 2018/12/18 14:24:02 visa Exp $ */ | 1/* $OpenBSD: octeonreg.h,v 1.10 2019/09/07 13:58:58 visa Exp $ */ |
| 2 3/* 4 * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com). 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright --- 162 unchanged lines hidden (view full) --- 172 173#define FPA3_CLK_COUNT 0x12800000000f0ULL 174 175/* OCTEON II */ 176#define MIO_RST_BOOT 0x1180000001600ULL 177#define MIO_RST_BOOT_PNR_MUL_SHIFT 24 178#define MIO_RST_BOOT_PNR_MUL_MASK 0x3f 179 | 2 3/* 4 * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com). 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright --- 162 unchanged lines hidden (view full) --- 172 173#define FPA3_CLK_COUNT 0x12800000000f0ULL 174 175/* OCTEON II */ 176#define MIO_RST_BOOT 0x1180000001600ULL 177#define MIO_RST_BOOT_PNR_MUL_SHIFT 24 178#define MIO_RST_BOOT_PNR_MUL_MASK 0x3f 179 |
| 180#define MIO_RST_CTL(x) (0x1180000001618ULL + 8 * (x)) 181#define MIO_RST_CTL_PRTMODE 0x0000000000000030ULL 182 |
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| 180/* OCTEON III */ 181#define RST_BOOT 0x1180006001600ULL 182#define RST_BOOT_PNR_MUL_SHIFT 24 183#define RST_BOOT_PNR_MUL_MASK 0x3f | 183/* OCTEON III */ 184#define RST_BOOT 0x1180006001600ULL 185#define RST_BOOT_PNR_MUL_SHIFT 24 186#define RST_BOOT_PNR_MUL_MASK 0x3f |
| 187#define RST_CTL(x) (0x1180006001640ULL + 8 * (x)) 188#define RST_CTL_RST_DONE 0x0000000000000100ULL 189#define RST_CTL_HOST_MODE 0x0000000000000040ULL |
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| 184#define RST_SOFT_RST 0x1180006001680ULL 185 186#define OCTEON_IO_REF_CLOCK 50000000 /* 50MHz */ 187 188#endif /* !_MACHINE_OCTEONREG_H_ */ | 190#define RST_SOFT_RST 0x1180006001680ULL 191 192#define OCTEON_IO_REF_CLOCK 50000000 /* 50MHz */ 193 194#endif /* !_MACHINE_OCTEONREG_H_ */ |