digic.c (9fc7fc4d) digic.c (db873cc5)
1/*
2 * QEMU model of the Canon DIGIC SoC.
3 *
4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5 *
6 * This model is based on reverse engineering efforts
7 * made by CHDK (http://chdk.wikia.com) and
8 * Magic Lantern (http://www.magiclantern.fm) projects

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38
39 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
40
41 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
42#define DIGIC_TIMER_NAME_MLEN 11
43 char name[DIGIC_TIMER_NAME_MLEN];
44
45 snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
1/*
2 * QEMU model of the Canon DIGIC SoC.
3 *
4 * Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
5 *
6 * This model is based on reverse engineering efforts
7 * made by CHDK (http://chdk.wikia.com) and
8 * Magic Lantern (http://www.magiclantern.fm) projects

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38
39 object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946"));
40
41 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
42#define DIGIC_TIMER_NAME_MLEN 11
43 char name[DIGIC_TIMER_NAME_MLEN];
44
45 snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
46 sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
47 TYPE_DIGIC_TIMER);
46 object_initialize_child(obj, name, &s->timer[i], TYPE_DIGIC_TIMER);
48 }
49
47 }
48
50 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
51 TYPE_DIGIC_UART);
49 object_initialize_child(obj, "uart", &s->uart, TYPE_DIGIC_UART);
52}
53
54static void digic_realize(DeviceState *dev, Error **errp)
55{
56 DigicState *s = DIGIC(dev);
57 Error *err = NULL;
58 SysBusDevice *sbd;
59 int i;

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66
67 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
68 if (err != NULL) {
69 error_propagate(errp, err);
70 return;
71 }
72
73 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
50}
51
52static void digic_realize(DeviceState *dev, Error **errp)
53{
54 DigicState *s = DIGIC(dev);
55 Error *err = NULL;
56 SysBusDevice *sbd;
57 int i;

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64
65 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
66 if (err != NULL) {
67 error_propagate(errp, err);
68 return;
69 }
70
71 for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
74 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
72 sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
75 if (err != NULL) {
76 error_propagate(errp, err);
77 return;
78 }
79
80 sbd = SYS_BUS_DEVICE(&s->timer[i]);
81 sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
82 }
83
84 qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
73 if (err != NULL) {
74 error_propagate(errp, err);
75 return;
76 }
77
78 sbd = SYS_BUS_DEVICE(&s->timer[i]);
79 sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i));
80 }
81
82 qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0));
85 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
83 sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
86 if (err != NULL) {
87 error_propagate(errp, err);
88 return;
89 }
90
91 sbd = SYS_BUS_DEVICE(&s->uart);
92 sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
93}

--- 24 unchanged lines hidden --- 		84 if (err != NULL) {
85 error_propagate(errp, err);
86 return;
87 }
88
89 sbd = SYS_BUS_DEVICE(&s->uart);
90 sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE);
91}

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