nrf51_soc.c (9bdee7f4) nrf51_soc.c (db873cc5)
1/*
2 * Nordic Semiconductor nRF51 SoC
3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
4 *
5 * Copyright 2018 Joel Stanley <joel@jms.id.au>
6 *
7 * This code is licensed under the GPL version 2 or later. See
8 * the COPYING file in the top-level directory.

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66 }
67
68 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
69 &err);
70 if (err) {
71 error_propagate(errp, err);
72 return;
73 }
1/*
2 * Nordic Semiconductor nRF51 SoC
3 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
4 *
5 * Copyright 2018 Joel Stanley <joel@jms.id.au>
6 *
7 * This code is licensed under the GPL version 2 or later. See
8 * the COPYING file in the top-level directory.

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66 }
67
68 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
69 &err);
70 if (err) {
71 error_propagate(errp, err);
72 return;
73 }
74 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
74 sysbus_realize(SYS_BUS_DEVICE(&s->cpu), &err);
75 if (err) {
76 error_propagate(errp, err);
77 return;
78 }
79
80 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
81
82 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
83 &err);
84 if (err) {
85 error_propagate(errp, err);
86 return;
87 }
88 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
89
90 /* UART */
75 if (err) {
76 error_propagate(errp, err);
77 return;
78 }
79
80 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
81
82 memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
83 &err);
84 if (err) {
85 error_propagate(errp, err);
86 return;
87 }
88 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
89
90 /* UART */
91 object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
91 sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);
92 if (err) {
93 error_propagate(errp, err);
94 return;
95 }
96 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
97 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
98 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
99 qdev_get_gpio_in(DEVICE(&s->cpu),
100 BASE_TO_IRQ(NRF51_UART_BASE)));
101
102 /* RNG */
92 if (err) {
93 error_propagate(errp, err);
94 return;
95 }
96 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
97 memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
98 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
99 qdev_get_gpio_in(DEVICE(&s->cpu),
100 BASE_TO_IRQ(NRF51_UART_BASE)));
101
102 /* RNG */
103 object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
103 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &err);
104 if (err) {
105 error_propagate(errp, err);
106 return;
107 }
108
109 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
110 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
111 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
112 qdev_get_gpio_in(DEVICE(&s->cpu),
113 BASE_TO_IRQ(NRF51_RNG_BASE)));
114
115 /* UICR, FICR, NVMC, FLASH */
116 object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
117 &err);
118 if (err) {
119 error_propagate(errp, err);
120 return;
121 }
122
104 if (err) {
105 error_propagate(errp, err);
106 return;
107 }
108
109 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
110 memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
111 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
112 qdev_get_gpio_in(DEVICE(&s->cpu),
113 BASE_TO_IRQ(NRF51_RNG_BASE)));
114
115 /* UICR, FICR, NVMC, FLASH */
116 object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
117 &err);
118 if (err) {
119 error_propagate(errp, err);
120 return;
121 }
122
123 object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
123 sysbus_realize(SYS_BUS_DEVICE(&s->nvm), &err);
124 if (err) {
125 error_propagate(errp, err);
126 return;
127 }
128
129 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
130 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
131 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
132 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
133 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
134 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
135 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
136 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
137
138 /* GPIO */
124 if (err) {
125 error_propagate(errp, err);
126 return;
127 }
128
129 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
130 memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
131 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
132 memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
133 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
134 memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
135 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
136 memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
137
138 /* GPIO */
139 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
139 sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
140 if (err) {
141 error_propagate(errp, err);
142 return;
143 }
144
145 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
146 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
147
148 /* Pass all GPIOs to the SOC layer so they are available to the board */
149 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
150
151 /* TIMER */
152 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
153 object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
154 if (err) {
155 error_propagate(errp, err);
156 return;
157 }
140 if (err) {
141 error_propagate(errp, err);
142 return;
143 }
144
145 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
146 memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
147
148 /* Pass all GPIOs to the SOC layer so they are available to the board */
149 qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
150
151 /* TIMER */
152 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
153 object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
154 if (err) {
155 error_propagate(errp, err);
156 return;
157 }
158 object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
158 sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err);
159 if (err) {
160 error_propagate(errp, err);
161 return;
162 }
163
164 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
165
166 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);

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184static void nrf51_soc_init(Object *obj)
185{
186 uint8_t i = 0;
187
188 NRF51State *s = NRF51_SOC(obj);
189
190 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
191
159 if (err) {
160 error_propagate(errp, err);
161 return;
162 }
163
164 base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE;
165
166 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);

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184static void nrf51_soc_init(Object *obj)
185{
186 uint8_t i = 0;
187
188 NRF51State *s = NRF51_SOC(obj);
189
190 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
191
192 sysbus_init_child_obj(OBJECT(s), "armv6m", &s->cpu, sizeof(s->cpu),
193 TYPE_ARMV7M);
192 object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
194 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
195 ARM_CPU_TYPE_NAME("cortex-m0"));
196 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
197
193 qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
194 ARM_CPU_TYPE_NAME("cortex-m0"));
195 qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
196
198 sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
199 TYPE_NRF51_UART);
197 object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
200 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
201
198 object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
199
202 sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
203 TYPE_NRF51_RNG);
200 object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG);
204
201
205 sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
202 object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM);
206
203
207 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
208 TYPE_NRF51_GPIO);
204 object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO);
209
210 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
205
206 for (i = 0; i < NRF51_NUM_TIMERS; i++) {
211 sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
212 sizeof(s->timer[i]), TYPE_NRF51_TIMER);
207 object_initialize_child(obj, "timer[*]", &s->timer[i],
208 TYPE_NRF51_TIMER);
213
214 }
215}
216
217static Property nrf51_soc_properties[] = {
218 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
219 MemoryRegion *),
220 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),

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210 }
211}
212
213static Property nrf51_soc_properties[] = {
214 DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
215 MemoryRegion *),
216 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),

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