cpu-features.h (1036ce4e) cpu-features.h (5a534314)
1/*
2 * QEMU Arm CPU -- feature test functions
3 *
4 * Copyright (c) 2023 Linaro Ltd
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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446 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
447}
448
449static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
450{
451 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
452}
453
1/*
2 * QEMU Arm CPU -- feature test functions
3 *
4 * Copyright (c) 2023 Linaro Ltd
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either

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446 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
447}
448
449static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
450{
451 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
452}
453
454static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
455{
456 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
457}
458
459static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
460{
461 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
462}
463
464static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
465{
466 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
467}
468
469static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
470{
471 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;

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519{
520 /*
521 * Return true if pauth is enabled with the architected QARMA3 algorithm.
522 * QEMU will always enable or disable both APA3 and GPA3.
523 */
524 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
525}
526
454static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
455{
456 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
457}
458
459static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
460{
461 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;

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509{
510 /*
511 * Return true if pauth is enabled with the architected QARMA3 algorithm.
512 * QEMU will always enable or disable both APA3 and GPA3.
513 */
514 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
515}
516
517static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
518{
519 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
520}
521
522static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
523{
524 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
525}
526
527static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
528{
529 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
530}
531
532static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
533{
534 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;

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549 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
550}
551
552static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
553{
554 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
555}
556
527static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
528{
529 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
530}
531
532static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
533{
534 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;

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549 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
550}
551
552static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
553{
554 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
555}
556
557static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
558{
559 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
560}
561
562static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
563{
564 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
565}
566
567static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
568{
569 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
570}
571
572static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
573{
574 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
575}
576
577static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
578{
579 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
580}
581
582static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
583{
584 /* We always set the AdvSIMD and FP fields identically. */
585 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
586}
587
588static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
589{

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626 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
627}
628
629static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
630{
631 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
632}
633
557static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
558{
559 /* We always set the AdvSIMD and FP fields identically. */
560 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
561}
562
563static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
564{

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601 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
602}
603
604static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
605{
606 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
607}
608
634static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
609static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
635{
610{
636 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
611 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
637}
638
612}
613
639static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
614static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
640{
615{
641 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
642 if (key >= 2) {
643 return true; /* FEAT_CSV2_2 */
644 }
645 if (key == 1) {
646 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
647 return key >= 2; /* FEAT_CSV2_1p2 */
648 }
649 return false;
616 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
650}
651
617}
618
652static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
619static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
653{
620{
654 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
621 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
655}
656
622}
623
657static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
624static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
658{
625{
659 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
626 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
660}
661
627}
628
662static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
629static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
663{
630{
664 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
631 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
665}
666
632}
633
667static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
634static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
668{
635{
669 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
636 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
670}
671
637}
638
672static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
639static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
673{
640{
674 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
641 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
675}
676
642}
643
677static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
644static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
678{
645{
679 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
646 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
680}
681
647}
648
682static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
649static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
683{
650{
684 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
685 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
651 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
686}
687
652}
653
688static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
654static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
689{
655{
690 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
656 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
691}
692
657}
658
693static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
659static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
694{
660{
695 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
696 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
661 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
697}
698
662}
663
699static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
664static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
700{
665{
701 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
666 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
702}
703
667}
668
704static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
669static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
705{
670{
706 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
671 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
707}
708
672}
673
709static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
674static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
710{
675{
711 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
676 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
712}
713
677}
678
714static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
679static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
715{
680{
716 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
717 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
681 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
718}
719
682}
683
720static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
684static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
721{
685{
722 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
723 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
686 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
724}
725
687}
688
726static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
689static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
727{
690{
728 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
729 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
691 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
730}
731
692}
693
732static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
694static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
733{
695{
734 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
696 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
735}
736
697}
698
737static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
699static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
738{
700{
739 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
701 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
702 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
740}
741
703}
704
742static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
705static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
743{
706{
744 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
707 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
708 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
745}
746
709}
710
747static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
711static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
748{
712{
749 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
713 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
714 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
750}
751
715}
716
752static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
717static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
753{
718{
754 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
719 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
755}
756
720}
721
757static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
722static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
758{
723{
759 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
724 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
760}
761
725}
726
762static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
727static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
763{
728{
764 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
729 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
765}
766
730}
731
767static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
732static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
768{
733{
769 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
734 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
770}
771
735}
736
772static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
737static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
773{
738{
774 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
739 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
775}
776
740}
741
777static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
742static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
778{
743{
779 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
744 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
745 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
780}
781
746}
747
782static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
748static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
783{
749{
784 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
750 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
785}
786
751}
752
787static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
753static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
788{
754{
789 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
755 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
756 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
790}
791
757}
758
792static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
759static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
793{
760{
794 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
761 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
795}
796
762}
763
797static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
764static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
798{
765{
799 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
766 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
800}
801
767}
768
802static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
769static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
803{
770{
804 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
771 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
805}
806
772}
773
807static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
774static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
808{
775{
809 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
776 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
777 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
810}
811
778}
779
812static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
780static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
813{
781{
814 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
782 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
783 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
815}
816
784}
785
817static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
786static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
818{
787{
819 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
788 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
789 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
820}
821
790}
791
792static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
793{
794 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
795}
796
822static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
823{
824 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
825}
826
827static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
828{
829 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
830}
831
832static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
833{
834 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
835}
836
797static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
798{
799 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
800}
801
802static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
803{
804 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
805}
806
807static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
808{
809 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
810}
811
837static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
812static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
838{
813{
839 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
840 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
814 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
841}
842
815}
816
843static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
817static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
844{
818{
845 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
846 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
819 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
847}
848
820}
821
849static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
822static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
850{
823{
851 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
852 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
824 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
853}
854
825}
826
855static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
827static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
856{
828{
857 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
829 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
858}
859
830}
831
860static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
832static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
861{
833{
862 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
834 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
835 if (key >= 2) {
836 return true; /* FEAT_CSV2_2 */
837 }
838 if (key == 1) {
839 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
840 return key >= 2; /* FEAT_CSV2_1p2 */
841 }
842 return false;
863}
864
843}
844
845static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
846{
847 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
848}
849
850static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
851{
852 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
853}
854
865static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
866{
867 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
868}
869
870static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
871{
872 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;

--- 49 unchanged lines hidden (view full) ---

922 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
923}
924
925static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
926{
927 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
928}
929
855static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
856{
857 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
858}
859
860static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
861{
862 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;

--- 49 unchanged lines hidden (view full) ---

912 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
913}
914
915static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
916{
917 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
918}
919
920static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
921{
922 return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
923}
924
925static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
926{
927 return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
928}
929
930/*
931 * Feature tests for "does this exist in either 32-bit or 64-bit?"
932 */
933static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
934{
935 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
936}
937

--- 57 unchanged lines hidden --- 		930/*
931 * Feature tests for "does this exist in either 32-bit or 64-bit?"
932 */
933static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
934{
935 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
936}
937

--- 57 unchanged lines hidden ---