#
39695e15 |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_fp macro
msr_fp macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Rich
target/ppc: Remove msr_fp macro
msr_fp macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-13-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
c354d858 |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_me macro
msr_me macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Rich
target/ppc: Remove msr_me macro
msr_me macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-11-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
8e54ad65 |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_pow macro
msr_pow macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Ri
target/ppc: Remove msr_pow macro
msr_pow macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-10-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
acc861c2 |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_ce macro
msr_ce macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Rich
target/ppc: Remove msr_ce macro
msr_ce macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
0939b8f8 |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_ee macro
msr_ee macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Rich
target/ppc: Remove msr_ee macro
msr_ee macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-8-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
d41ccf6e |
| 04-May-2022 |
Víctor Colombo <victor.colombo@eldorado.org.br> |
target/ppc: Remove msr_pr macro
msr_pr macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Rich
target/ppc: Remove msr_pr macro
msr_pr macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
d3412df2 |
| 02-Mar-2022 |
Daniel Henrique Barboza <danielhb413@gmail.com> |
target/ppc: trigger PERFM EBBs from power8-pmu.c
This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and
target/ppc: trigger PERFM EBBs from power8-pmu.c
This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event.
If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
cb76bbc4 |
| 02-Mar-2022 |
Daniel Henrique Barboza <danielhb413@gmail.com> |
target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem st
target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB exception. They are being added as POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that occurred and trigger the appropriate exception. Both exceptions are doing the same thing in this first implementation: clear BESCR_GE and enter the branch with env->nip retrieved from SPR_EBBHR.
The checks being done by the interrupt code are msr_pr and BESCR_GE states. All other checks (EBB facility check, BESCR_PME bit, specific bits related to the event type) must be done beforehand.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220225101140.1054160-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
cd617484 |
| 07-Feb-2022 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
exec/exec-all: Move 'qemu/log.h' include in units requiring it
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core
exec/exec-all: Move 'qemu/log.h' include in units requiring it
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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#
7cebc5db |
| 18-Feb-2022 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Introduce a vhyp framework for nested HV support
Introduce virtual hypervisor methods that can support a "Nested KVM HV" implementation using the bare metal 2-level radix MMU, and using
target/ppc: Introduce a vhyp framework for nested HV support
Introduce virtual hypervisor methods that can support a "Nested KVM HV" implementation using the bare metal 2-level radix MMU, and using HV exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG spapr machine when running a nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr, hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts.
HV exceptions are intercepted in the exception handler code and instead of causing interrupts in the guest and switching the machine to HV mode, they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the interrupt vector numer as return value as required by the hcall API.
Address translation is provided by the 2-level page table walker that is implemented for the bare metal radix MMU. The partition scope page table is pointed to the L1's partition scope by the get_pate vhc method.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220216102545.1808018-9-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
3680e994 |
| 18-Feb-2022 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add powerpc_reset_excp_state helper
This moves the logic to reset the QEMU exception state into its own function.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Pi
target/ppc: Add powerpc_reset_excp_state helper
This moves the logic to reset the QEMU exception state into its own function.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-8-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
4c6cf6b2 |
| 18-Feb-2022 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: add helper for books vhyp hypercall handler
The virtual hypervisor currently always intercepts and handles hypercalls but with a future change this will not always be the case.
Add a he
target/ppc: add helper for books vhyp hypercall handler
The virtual hypervisor currently always intercepts and handles hypercalls but with a future change this will not always be the case.
Add a helper for the test so the logic is abstracted from the mechanism.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220216102545.1808018-7-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
10895ab6 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
We don't really need to check for exception model while applying AIL. We can check the lpcr_mask for the presence of LPCR_AIL/LP
target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
We don't really need to check for exception model while applying AIL. We can check the lpcr_mask for the presence of LPCR_AIL/LPCR_HAIL.
This removes one more instance of passing the exception model ID around.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
fce9fbaf |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: Assert if MSR bits differ from msr_mask during exceptions
We currently abort QEMU during the dispatch of an interrupt if we try to set MSR_HV without having MSR_HVB in the msr_mask. I th
target/ppc: Assert if MSR bits differ from msr_mask during exceptions
We currently abort QEMU during the dispatch of an interrupt if we try to set MSR_HV without having MSR_HVB in the msr_mask. I think we should verify this for all MSR bits. There is no reason to ever have a MSR bit set if the corresponding bit is not set in that CPU's msr_mask.
Note that this is not about the emulated code setting reserved bits. We clear the new_msr when starting to dispatch an exception, so if we end up with bits not present in the msr_mask that is a QEMU programming error.
I kept the HSRR verification for BookS because it is the only CPU family that has HSRRs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
c6eaac89 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: powerpc_excp: Move common code to the caller function
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving the bounds check and logging to powerpc_excp.
Signed-off-by:
target/ppc: powerpc_excp: Move common code to the caller function
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving the bounds check and logging to powerpc_excp.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
28091374 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: Remove powerpc_excp_legacy
Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy.
Signed-off-by: Fabiano Rosas <farosas@linux.ib
target/ppc: Remove powerpc_excp_legacy
Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
fe4b5c4c |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: Set SRRs directly in exception code
The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <far
target/ppc: 7xx: Set SRRs directly in exception code
The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
7df40c54 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: Software TLB cleanup
This code applies only to the 7xx CPUs, so we can remove the switch statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430
target/ppc: 7xx: Software TLB cleanup
This code applies only to the 7xx CPUs, so we can remove the switch statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
3c3fa438 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: System Reset cleanup
Thre is no HV support in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com> Signed-off-
target/ppc: 7xx: System Reset cleanup
Thre is no HV support in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
3b578635 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: System Call exception cleanup
Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode.
Signed-
target/ppc: 7xx: System Call exception cleanup
Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
ab369390 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: Program exception cleanup
There's no ESR in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com> Signed-off-by
target/ppc: 7xx: Program exception cleanup
There's no ESR in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
a53ce465 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: External interrupt cleanup
There is no MSR_HV in the 7xx so remove the LPES0 handling.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-6-fa
target/ppc: 7xx: External interrupt cleanup
There is no MSR_HV in the 7xx so remove the LPES0 handling.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
784f5a34 |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: 7xx: Machine Check exception cleanup
There's no MSR_HV in the 7xx.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457
target/ppc: 7xx: Machine Check exception cleanup
There's no MSR_HV in the 7xx.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
93848d6a |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: Simplify powerpc_excp_7xx
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hy
target/ppc: Simplify powerpc_excp_7xx
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DLTLB POWERPC_EXCP_DSI POWERPC_EXCP_DSTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_IFTLB POWERPC_EXCP_ISI POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_THERM POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
ccfca2fc |
| 09-Feb-2022 |
Fabiano Rosas <farosas@linux.ibm.com> |
target/ppc: Introduce powerpc_excp_7xx
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy ve
target/ppc: Introduce powerpc_excp_7xx
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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