Lines Matching +refs:def +refs:add +refs:sub +refs:carry
17 def ARMtsecall : SDNode<"ARMISD::tSECALL", SDT_ARMcall,
21 def imm_sr_XFORM: SDNodeXForm<imm, [{
25 def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }
26 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
38 def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; }
39 def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{
46 def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; }
47 def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{
55 def imm0_255_comp : PatLeaf<(i32 imm), [{
59 def imm8_255_neg : PatLeaf<(i32 imm), [{
67 def thumb_immshifted : PatLeaf<(imm), [{
71 def thumb_immshifted_val : SDNodeXForm<imm, [{
76 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
81 def imm256_510 : ImmLeaf<i32, [{
85 def thumb_imm256_510_addend : SDNodeXForm<imm, [{
90 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
91 def t_imm0_1020s4 : Operand<i32> {
97 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
98 def t_imm0_508s4 : Operand<i32> {
104 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
105 def t_imm0_508s4_neg : Operand<i32> {
118 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
123 def ThumbMemPC : AsmOperandClass {
128 def t_brtarget : Operand<OtherVT> {
134 def t_adrlabel : Operand<i32> {
141 def thumb_br_target : Operand<OtherVT> {
147 def thumb_bl_target : Operand<i32> {
154 def thumb_blx_target : Operand<i32> {
160 def thumb_bcc_target : Operand<OtherVT> {
166 def thumb_cb_target : Operand<OtherVT> {
175 def t_addrmode_pc : MemOperand {
184 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
185 def t_addrmode_rr : MemOperand,
198 def t_addrmode_rr_sext : MemOperand,
214 def t_addrmode_rrs1 : MemOperand,
222 def t_addrmode_rrs2 : MemOperand,
230 def t_addrmode_rrs4 : MemOperand,
241 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
242 def t_addrmode_is4 : MemOperand,
253 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
254 def t_addrmode_is2 : MemOperand,
265 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
266 def t_addrmode_is1 : MemOperand,
279 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
280 def t_addrmode_sp : MemOperand,
290 // an add (i.e. whether we know overflow won't occur in the add).
291 def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [],
295 def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
305 def tADJCALLSTACKUP :
310 def tADJCALLSTACKDOWN :
322 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
335 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
336 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
337 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
338 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
339 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
340 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
346 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
355 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
357 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
364 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
375 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
390 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
403 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
404 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
416 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
423 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
424 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
434 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
435 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
443 def : tInstSubst<"add${p} sp, $imm",
445 def : tInstSubst<"add${p} sp, sp, $imm",
449 def : tInstAlias<"add${p} sp, sp, $imm",
451 def : tInstAlias<"sub${p} sp, sp, $imm",
455 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
456 "add", "\t$Rdn, $sp, $Rn", []>,
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
492 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
503 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
507 def tBXNS_RET : tPseudoInst<(outs), (ins), 2, IIC_Br,
511 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
522 def tBL : TIx2<0b11110, 0b11, 1,
536 def tBLXi : TIx2<0b11110, 0b11, 0,
550 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
558 def tBLXr_noip : ARMPseudoExpand<(outs), (ins pred:$p, GPRnoip:$func),
565 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
575 def tBLXNS_CALL : PseudoInst<(outs), (ins GPRnopc:$func), IIC_Br,
580 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
587 def tBL_PUSHLR : tPseudoInst<(outs), (ins GPRlr:$ra, pred:$p, thumb_bl_target:$func),
593 def : ARMPat<(ARMcall GPR:$func), (tBLXr $func)>,
595 def : ARMPat<(ARMcall GPRnoip:$func), (tBLXr_noip $func)>,
600 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
612 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p),
617 def tBR_JTr : tPseudoInst<(outs),
631 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,
647 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
656 def tTAILJMPdND : tPseudoExpand<(outs),
669 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
679 def tTRAP : TI<(outs), (ins), IIC_Br,
692 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
706 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
726 def i : // reg/imm5
732 def r : // reg/reg
744 def i : // reg/imm5
749 def r : // reg/reg
775 def tLDRSB : // A8.6.80
782 def tLDRSH : // A8.6.84
789 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
826 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
838 def tLDMIA_UPD :
853 def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),
866 def : InstAlias<"ldm${p} $Rn!, $regs",
872 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
882 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
967 // Add with carry register
969 def tADC : // A8.6.2
975 def tADDi3 : // A8.6.4 T1
978 "add", "\t$Rd, $Rm, $imm3",
979 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
985 def tADDi8 : // A8.6.4 T2
988 "add", "\t$Rdn, $imm8",
989 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
994 def tADDrr : // A8.6.6 T1
997 "add", "\t$Rd, $Rn, $Rm",
998 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1007 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1014 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1021 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1029 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1038 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
1039 "add", "\t$Rdn, $Rm", []>,
1052 def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
1054 def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
1056 def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
1059 def : tInstAlias <"add${s}${p} $Rdn, $Rm",
1062 def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
1064 def : tInstSubst<"sub${s}${p} $rdn, $imm",
1070 def tAND : // A8.6.12
1077 def tASRri : // A8.6.14
1088 def tASRrr : // A8.6.15
1095 def tBIC : // A8.6.20
1106 //def tCMN : // A8.6.33
1112 def tCMNz : // A8.6.33
1122 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1134 def tCMPr : // A8.6.36 T1
1140 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1155 def tEOR : // A8.6.45
1162 def tLSLri : // A8.6.88
1173 def tLSLrr : // A8.6.89
1180 def tLSRri : // A8.6.90
1191 def tLSRrr : // A8.6.91
1199 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1211 def : tInstAlias <"movs $Rdn, $imm",
1217 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1229 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1242 def tMUL : // A8.6.105 T1
1254 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1258 def tMVN : // A8.6.107
1265 def tORR : // A8.6.114
1272 def tREV : // A8.6.134
1279 def tREV16 : // A8.6.135
1286 def tREVSH : // A8.6.136
1294 def tROR : // A8.6.139
1302 def tRSB : // A8.6.141
1308 // Subtract with carry register
1310 def tSBC : // A8.6.151
1318 def tSUBi3 : // A8.6.210 T1
1321 "sub", "\t$Rd, $Rm, $imm3",
1322 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1328 def tSUBi8 : // A8.6.210 T2
1331 "sub", "\t$Rdn, $imm8",
1332 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1335 def : tInstSubst<"add${s}${p} $rd, $rn, $imm",
1339 def : tInstSubst<"add${s}${p} $rdn, $imm",
1344 def tSUBrr : // A8.6.212
1347 "sub", "\t$Rd, $Rn, $Rm",
1348 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1351 def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
1361 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1368 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1375 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1382 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1389 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
1395 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1403 def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>;
1404 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>;
1405 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>;
1409 def tSXTB : // A8.6.222
1418 def tSXTH : // A8.6.224
1428 def tTST : // A8.6.230
1435 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1443 def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>;
1444 def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>;
1446 def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",
1454 def tUXTB : // A8.6.262
1463 def tUXTH : // A8.6.264
1473 def tMOVCCr_pseudo :
1481 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1492 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1496 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1504 def tTBB_JT : tPseudoInst<(outs),
1508 def tTBH_JT : tPseudoInst<(outs),
1521 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1542 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1549 def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),
1558 def tInt_WIN_eh_sjlj_longjmp
1568 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1570 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1574 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1576 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),
1578 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1581 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1586 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1589 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1595 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1602 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
1605 def : Pat<(ARMWrapper tglobaltlsaddr:$addr),
1611 def : T1Pat<(ARMWrapperJT tjumptable:$dst),
1615 def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
1619 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1621 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),
1628 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1630 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1632 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1636 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1637 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1638 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1639 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1640 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1641 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
1650 def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb),
1655 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
1658 def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4),
1665 def : T1Pat<(sextloadi8 tGPR:$Rn),
1668 def : T1Pat<(sextloadi16 tGPR:$Rn),
1673 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1675 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1677 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1679 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1682 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1684 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1686 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1688 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1690 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1692 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1694 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1696 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val),
1698 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1700 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val),
1702 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1704 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val),
1710 def : T1Pat<(i32 thumb_immshifted:$src),
1714 def : T1Pat<(i32 imm0_255_comp:$src),
1717 def : T1Pat<(i32 imm256_510:$src),
1721 // Pseudo instruction that combines ldr from constpool and add pc. This should
1725 def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1735 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1741 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1749 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
1753 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1758 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1760 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1762 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1766 def tLDRConstPool
1779 def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
1783 def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),