Lines Matching +refs:def +refs:add +refs:sub +refs:carry
17 def ARMtsecall : SDNode<"ARMISD::tSECALL", SDT_ARMcall,
21 def imm_sr_XFORM: SDNodeXForm<imm, [{
25 def ThumbSRImmAsmOperand: ImmAsmOperand<1,32> { let Name = "ImmThumbSR"; }
26 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
38 def ThumbModImmNeg1_7AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg1_7"; }
39 def mod_imm1_7_neg : Operand<i32>, PatLeaf<(imm), [{
46 def ThumbModImmNeg8_255AsmOperand : AsmOperandClass { let Name = "ThumbModImmNeg8_255"; }
47 def mod_imm8_255_neg : Operand<i32>, PatLeaf<(imm), [{
55 def imm0_255_comp : PatLeaf<(i32 imm), [{
59 def imm8_255_neg : PatLeaf<(i32 imm), [{
67 def thumb_immshifted : PatLeaf<(imm), [{
71 def thumb_immshifted_val : SDNodeXForm<imm, [{
76 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
81 def imm256_510 : ImmLeaf<i32, [{
85 def thumb_imm256_510_addend : SDNodeXForm<imm, [{
90 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
91 def t_imm0_1020s4 : Operand<i32> {
97 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
98 def t_imm0_508s4 : Operand<i32> {
104 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
105 def t_imm0_508s4_neg : Operand<i32> {
118 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
123 def ThumbMemPC : AsmOperandClass {
128 def t_brtarget : Operand<OtherVT> {
134 def t_adrlabel : Operand<i32> {
141 def thumb_br_target : Operand<OtherVT> {
147 def thumb_bl_target : Operand<i32> {
154 def thumb_blx_target : Operand<i32> {
160 def thumb_bcc_target : Operand<OtherVT> {
166 def thumb_cb_target : Operand<OtherVT> {
174 def t_addrmode_pc : MemOperand {
184 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
185 def t_addrmode_rr : MemOperand,
198 def t_addrmode_rr_sext : MemOperand,
214 def t_addrmode_rrs1 : MemOperand,
222 def t_addrmode_rrs2 : MemOperand,
230 def t_addrmode_rrs4 : MemOperand,
241 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
242 def t_addrmode_is4 : MemOperand,
253 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
254 def t_addrmode_is2 : MemOperand,
265 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
266 def t_addrmode_is1 : MemOperand,
279 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
280 def t_addrmode_sp : MemOperand,
290 // an add (i.e. whether we know overflow won't occur in the add).
291 def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [],
295 def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
305 def tADJCALLSTACKUP :
310 def tADJCALLSTACKDOWN :
322 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
335 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
336 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
337 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
338 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
339 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
340 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
346 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
355 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
357 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
364 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
375 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
390 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
403 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
404 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
416 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
423 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
424 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
434 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
435 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
443 def : tInstSubst<"add${p} sp, $imm",
445 def : tInstSubst<"add${p} sp, sp, $imm",
449 def : tInstAlias<"add${p} sp, sp, $imm",
451 def : tInstAlias<"sub${p} sp, sp, $imm",
455 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
456 "add", "\t$Rdn, $sp, $Rn", []>,
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
492 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>,
503 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
507 def tBXNS_RET : tPseudoInst<(outs), (ins), 2, IIC_Br,
511 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
522 def tBL : TIx2<0b11110, 0b11, 1,
536 def tBLXi : TIx2<0b11110, 0b11, 0,
550 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
561 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br,
571 def tBLXNS_CALL : PseudoInst<(outs), (ins GPRnopc:$func), IIC_Br,
576 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
583 def tBL_PUSHLR : tPseudoInst<(outs), (ins GPRlr:$ra, pred:$p, thumb_bl_target:$func),
591 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
603 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p),
608 def tBR_JTr : tPseudoInst<(outs),
622 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br,
638 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
647 def tTAILJMPdND : tPseudoExpand<(outs),
660 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
670 def tTRAP : TI<(outs), (ins), IIC_Br,
683 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
697 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
717 def i : // reg/imm5
723 def r : // reg/reg
735 def i : // reg/imm5
740 def r : // reg/reg
766 def tLDRSB : // A8.6.80
773 def tLDRSH : // A8.6.84
780 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
817 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
829 def tLDMIA_UPD :
844 def tSTMIA_UPD : Thumb1I<(outs tGPR:$wb),
857 def : InstAlias<"ldm${p} $Rn!, $regs",
863 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
873 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
958 // Add with carry register
960 def tADC : // A8.6.2
966 def tADDi3 : // A8.6.4 T1
969 "add", "\t$Rd, $Rm, $imm3",
970 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
976 def tADDi8 : // A8.6.4 T2
979 "add", "\t$Rdn, $imm8",
980 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
985 def tADDrr : // A8.6.6 T1
988 "add", "\t$Rd, $Rn, $Rm",
989 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
998 def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1005 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1012 def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1020 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1029 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
1030 "add", "\t$Rdn, $Rm", []>,
1043 def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
1045 def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
1047 def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
1050 def : tInstAlias <"add${s}${p} $Rdn, $Rm",
1053 def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
1055 def : tInstSubst<"sub${s}${p} $rdn, $imm",
1061 def tAND : // A8.6.12
1068 def tASRri : // A8.6.14
1079 def tASRrr : // A8.6.15
1086 def tBIC : // A8.6.20
1097 //def tCMN : // A8.6.33
1103 def tCMNz : // A8.6.33
1113 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
1125 def tCMPr : // A8.6.36 T1
1131 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1146 def tEOR : // A8.6.45
1153 def tLSLri : // A8.6.88
1164 def tLSLrr : // A8.6.89
1171 def tLSRri : // A8.6.90
1182 def tLSRrr : // A8.6.91
1190 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1202 def : tInstAlias <"movs $Rdn, $imm",
1208 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1220 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1233 def tMUL : // A8.6.105 T1
1245 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1249 def tMVN : // A8.6.107
1256 def tORR : // A8.6.114
1263 def tREV : // A8.6.134
1270 def tREV16 : // A8.6.135
1277 def tREVSH : // A8.6.136
1285 def tROR : // A8.6.139
1293 def tRSB : // A8.6.141
1299 // Subtract with carry register
1301 def tSBC : // A8.6.151
1309 def tSUBi3 : // A8.6.210 T1
1312 "sub", "\t$Rd, $Rm, $imm3",
1313 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1319 def tSUBi8 : // A8.6.210 T2
1322 "sub", "\t$Rdn, $imm8",
1323 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1326 def : tInstSubst<"add${s}${p} $rd, $rn, $imm",
1330 def : tInstSubst<"add${s}${p} $rdn, $imm",
1335 def tSUBrr : // A8.6.212
1338 "sub", "\t$Rd, $Rn, $Rm",
1339 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1342 def : tInstAlias <"sub${s}${p} $Rdn, $Rm",
1352 def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1359 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1366 def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
1373 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1380 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
1386 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1394 def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>;
1395 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>;
1396 def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>;
1400 def tSXTB : // A8.6.222
1409 def tSXTH : // A8.6.224
1419 def tTST : // A8.6.230
1426 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1434 def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>;
1435 def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>;
1437 def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0",
1445 def tUXTB : // A8.6.262
1454 def tUXTH : // A8.6.264
1464 def tMOVCCr_pseudo :
1472 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1483 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1487 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1495 def tTBB_JT : tPseudoInst<(outs),
1499 def tTBH_JT : tPseudoInst<(outs),
1512 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1533 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1540 def tInt_eh_sjlj_longjmp : XI<(outs), (ins tGPR:$src, tGPR:$scratch),
1549 def tInt_WIN_eh_sjlj_longjmp
1559 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1561 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1565 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1567 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),
1569 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1572 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1577 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1580 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1586 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1593 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr),
1596 def : Pat<(ARMWrapper tglobaltlsaddr:$addr),
1602 def : T1Pat<(ARMWrapperJT tjumptable:$dst),
1606 def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
1610 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1612 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),
1619 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1621 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1623 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1627 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1628 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1629 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1630 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1631 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1632 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
1641 def tLDR_postidx: tPseudoInst<(outs tGPR:$Rt, tGPR:$Rn_wb),
1646 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
1649 def : T1Pat<(post_store tGPR:$Rt, tGPR:$Rn, 4),
1654 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1657 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1660 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1663 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1667 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1669 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1671 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1673 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1676 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1678 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1680 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1682 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1684 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1686 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1688 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1690 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val),
1692 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1694 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val),
1696 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1698 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val),
1704 def : T1Pat<(i32 thumb_immshifted:$src),
1708 def : T1Pat<(i32 imm0_255_comp:$src),
1711 def : T1Pat<(i32 imm256_510:$src),
1715 // Pseudo instruction that combines ldr from constpool and add pc. This should
1719 def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1729 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1735 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1743 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
1747 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1752 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1754 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1756 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1760 def tLDRConstPool