Lines Matching refs:unspec
196 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
205 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
214 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
223 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
232 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
243 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
253 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
263 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
273 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
282 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
291 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
302 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
310 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
327 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
335 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
345 (unspec [(const_int 0)] 509)]
355 (unspec [(const_int 0)] 510)]
365 (unspec [(const_int 0)] 511)]
375 (unspec [(const_int 0)] 512)]
385 (unspec [(const_int 0)] 513)]
395 (unspec [(const_int 0)] 514)]
405 (unspec [(const_int 0)] 515)]
415 (unspec [(const_int 0)] 516)]
425 (unspec [(const_int 0)] 517)]
435 (unspec [(const_int 0)] 518)]
548 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
557 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
566 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
574 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
584 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
594 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
604 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
633 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
642 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
700 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
716 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
724 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
732 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
740 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
748 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
756 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
764 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
772 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
800 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
828 ;; differentiating between them with RTL so use an unspec of const_int 0
835 (unspec [(const_int 0)] 544)]
845 (unspec [(const_int 0)] 545)]
855 (unspec [(const_int 0)] 546)]
865 (unspec [(const_int 0)] 547)]
875 (unspec [(const_int 0)] 548)]
885 (unspec [(const_int 0)] 549)]
895 (unspec [(const_int 0)] 550)]
905 (unspec [(const_int 0)] 551)]
915 (unspec [(const_int 0)] 552)]
925 (unspec [(const_int 0)] 553)]
935 (unspec [(const_int 0)] 554)]
945 (unspec [(const_int 0)] 555)]
953 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
962 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
965 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
973 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
976 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
984 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
987 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
995 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
998 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1006 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1009 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1017 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1020 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1028 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1031 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1039 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1042 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1050 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1052 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1060 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1069 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1072 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1080 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1083 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1091 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1093 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1101 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1110 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1114 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1122 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1126 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1134 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1137 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1145 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1155 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1159 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1167 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1171 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1179 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1182 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1190 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1193 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1201 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1203 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1211 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1220 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1224 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1232 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1236 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1244 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1247 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1255 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1258 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1266 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1269 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1277 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1280 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1288 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1291 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1299 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1302 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1310 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1313 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1321 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1324 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1332 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1341 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1343 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1351 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1354 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1362 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1365 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1373 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1375 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1383 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1392 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1396 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1404 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1408 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1416 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1420 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1428 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1438 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1442 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1450 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1454 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1462 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1465 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1473 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1476 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1484 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1486 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1494 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1503 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1507 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1515 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1519 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1527 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1536 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1545 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1547 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1555 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1564 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1566 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1574 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1583 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1586 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1594 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1603 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1615 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1632 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1635 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1643 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1646 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1654 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1658 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1666 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1670 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1678 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1681 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1689 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1692 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1700 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1702 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1710 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1719 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1723 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1731 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1735 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1743 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1746 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1754 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1757 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1765 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1767 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1775 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1784 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1787 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1795 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1798 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1806 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1808 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1816 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1825 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1829 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1837 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1841 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1849 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1852 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1860 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1870 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1873 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1881 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1884 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1892 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1894 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1902 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1920 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1923 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1931 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1933 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1944 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1952 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1954 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
1962 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1971 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1989 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1992 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2000 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2002 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2010 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2013 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2021 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2023 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2033 (unspec:V2SI [(match_dup 1)] 726))]
2061 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2069 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2079 (unspec [(const_int 0)] 686)]
2089 (unspec [(const_int 0)] 687)]
2099 (unspec [(const_int 0)] 688)]
2109 (unspec [(const_int 0)] 689)]
2119 (unspec [(const_int 0)] 690)]
2129 (unspec [(const_int 0)] 691)]
2139 (unspec [(const_int 0)] 692)]
2149 (unspec [(const_int 0)] 693)]
2159 (unspec [(const_int 0)] 694)]
2169 (unspec [(const_int 0)] 695)]
2179 (unspec [(const_int 0)] 696)]
2189 (unspec [(const_int 0)] 697)]
2199 (unspec [(const_int 0)] 698)]
2209 (unspec [(const_int 0)] 699)]
2597 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2620 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2737 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2740 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2748 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2751 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2759 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2761 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2769 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2771 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2779 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2782 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2790 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2792 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2800 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2803 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2811 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2814 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2822 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2824 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2832 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2834 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2842 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2844 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2852 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2855 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2863 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2865 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2873 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2875 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2883 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2885 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2893 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2896 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2904 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2906 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2914 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2916 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2924 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2926 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
2950 (unspec:CCFP
2965 (unspec:CCFP
2976 (unspec:CCFP
2987 (unspec:CCFP
2998 (unspec:CCFP
3009 (unspec:CCFP
3020 (unspec:CCFP
3033 (unspec:CCFP
3044 (unspec:CCFP
3055 (unspec:CCFP
3066 (unspec:CCFP
3077 (unspec:CCFP
3088 (unspec:CCFP
3101 (unspec:CCFP
3114 (unspec:CCFP
3127 (unspec:CCFP
3140 (unspec:CCFP
3153 (unspec:CCFP
3166 (unspec:CCFP
3180 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")