Lines Matching refs:LD1
52 ``LDR`` and ``LD1``
66 Big endian vector load using ``LD1``. Note that the lanes retain the correct ordering.
69 Because of this, the instruction ``LD1`` performs a vector load but performs byte swapping not on t…
71 It may seem that ``LD1`` should suffice to peform vector loads on a big endian machine. However the…
76 …2. The content of a vector register is the same *as if* it had been loaded with an ``LD1`` instruc…
78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…
109 …t one advantage over ``LD1`` and ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the ind…
124 …``uint16x4_t``, which is equivalent in register content, if we passed as ``LD1`` we'd break this c…
133 …LD1`` only requires it to be as aligned as the lane size. If we canonicalised on using ``LDR``, we…
143 | | ``LDR`` layout | ``LD1`` layout |
145 | Lane ordering | ``LDR + REV`` | ``LD1`` |
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
149 | Alignment for strict mode | ``LDR`` / ``LD1 + REV`` | ``LD1`` |
152 …s was worse than the changes that would have to be made to support ``LD1``, so ``LD1`` was chosen …
171 The main problem with the ``LD1`` solution is dealing with bitconverts (or bitcasts, or reinterpret…
179 This would produce a code sequence such as that in the figure on the right. The mismatched ``LD1`` …
183 …gister representation of the data to be *as if* it had just been loaded by a ``LD1`` of type ``Y``.
188 …LD1`` of type ``X`` (converting the in-register representation to the same as if it had been loade…
192 LD1 v0.4s, [x]