Target/AMDGPU/VOP2Instructions.td

139     def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
150     def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
162       def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
176       def _dpp  : VOP2_DPP_Pseudo <opName, P>;
189         def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
195           def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {
199           def _dpp  : VOP2_DPP_Pseudo <opName, P>;
202       def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
218     def : VOP2bInstAlias<ps, inst, OpName, "vcc_lo">;
221     def : VOP2bInstAlias<ps, inst, OpName, "vcc">;
233       def _e32 : VOP2_Pseudo <opName, P>,
237         def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
242         def _dpp  : VOP2_DPP_Pseudo <opName, P>;
245     def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
265     def : VOP2eInstAlias<ps, inst, "vcc_lo">;
268     def : VOP2eInstAlias<ps, inst, "vcc">;
283 def VOP_MADAK_F16 : VOP_MADAK <f16>;
284 def VOP_MADAK_F32 : VOP_MADAK <f32>;
295 def VOP_MADMK_F16 : VOP_MADMK <f16>;
296 def VOP_MADMK_F32 : VOP_MADMK <f32>;
342 def VOP_MAC_F16 : VOP_MAC <f16>;
343 def VOP_MAC_F32 : VOP_MAC <f32>;
345 def VOP_MAC_LEGACY_F32 : VOP_MAC <f32>;
347 def VOP_MAC_F64 : VOP_MAC <f64>;
356 def VOP_DOT_ACC_F32_V2F16 : VOP_DOT_ACC<f32, v2f16> {
361 def VOP_DOT_ACC_I32_I32   : VOP_DOT_ACC<i32, i32> {
367 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], 0, /*EnableClamp=*/1> {
381 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], 0, /*EnableClamp=*/1> {
416 def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableF32SrcMods=*/1> {
451 def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
466 def VOP_WRITELANE : VOPProfile<[i32, i32, i32, i32]> {
489 def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
528 def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, []>;
552 def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
556 def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
612 def : DivergentBinOp<srl, V_LSHRREV_B32_e64>;
613 def : DivergentBinOp<sra, V_ASHRREV_I32_e64>;
614 def : DivergentBinOp<shl, V_LSHLREV_B32_e64>;
617   def : DivergentClampingBinOp<add, V_ADD_U32_e64>;
618   def : DivergentClampingBinOp<sub, V_SUB_U32_e64>;
622 def : DivergentClampingBinOp<add, V_ADD_CO_U32_e64>;
623 def : DivergentClampingBinOp<sub, V_SUB_CO_U32_e64>;
626 def : DivergentBinOp<adde, V_ADDC_U32_e32>;
627 def : DivergentBinOp<sube, V_SUBB_U32_e32>;
644 def :  divergent_i64_BinOp <and, V_AND_B32_e32>;
645 def :  divergent_i64_BinOp <or,  V_OR_B32_e32>;
646 def :  divergent_i64_BinOp <xor, V_XOR_B32_e32>;
651 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
667 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
671 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
672 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
738   def : GCNPat<
744   def : GCNPat<
750   def : GCNPat<
756   def : GCNPat<
765 def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">;
768 def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">;
774 def V_FMAMK_F16 : VOP2_Pseudo <"v_fmamk_f16", VOP_MADMK_F16, [], "">;
777 def V_FMAAK_F16 : VOP2_Pseudo <"v_fmaak_f16", VOP_MADAK_F16, [], "">;
797 def : GCNPat<
802 def : GCNPat<
818 def : GCNPat <
823 def : GCNPat <
828 def : GCNPat <
836 // Undo sub x, c -> add x, -c canonicalization since c is more likely
839 def : GCNPat<
840   (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
847 def : GCNPat<
848   (i32 (zext (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)))),
852 defm : Arithmetic_i16_0Hi_Pats<add, V_ADD_U16_e64>;
854 defm : Arithmetic_i16_0Hi_Pats<sub, V_SUB_U16_e64>;
864 def : ZExt_i16_i1_Pat<zext>;
865 def : ZExt_i16_i1_Pat<anyext>;
867 def : GCNPat <
878 def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
879 def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
883 let AddedComplexity = 1 in { // Prefer over form with carry-out.
884 def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
885 def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
890 def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
891 def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
956     def _gfx10 :
962     def _gfx10 :
970     def _e32_gfx10 :
975     def _e64_gfx10 :
981     def _sdwa_gfx10 :
989     def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
995     def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(NAME#"_e32")> {
1003     def _e32_gfx10 :
1012     def _e64_gfx10 :
1024       def _sdwa_gfx10 :
1034       def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp")> {
1042       def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1052     def _e32_gfx10 :
1060     def _e64_gfx10 :
1070     def _sdwa_gfx10 :
1078     def _sdwa_w32_gfx10 :
1088     def _sdwa_w64_gfx10 :
1100     def _dpp_gfx10 :
1107     def _dpp_w32_gfx10 :
1115     def _dpp_w64_gfx10 :
1125     def _dpp8_gfx10 :
1132     def _dpp8_w32_gfx10 :
1140     def _dpp8_w64_gfx10 :
1151     def _e64_gfx10 :
1160     def _e64_gfx10 :
1217 // VOP2 no carry-in, carry-out.
1225 // VOP2 carry-in, carry-out.
1247 // VOP3 carry-out.
1280     def _gfx6_gfx7 :
1285     def _gfx6_gfx7 :
1290     def _e32_gfx6_gfx7 :
1295     def _e64_gfx6_gfx7 :
1300     def _e64_gfx6_gfx7 :
1370   def : VOP2e64InstAlias<V_ADD_CO_U32_e64, V_ADD_I32_e64_gfx6_gfx7>;
1371   def : VOP2e64InstAlias<V_SUB_CO_U32_e64, V_SUB_I32_e64_gfx6_gfx7>;
1372   def : VOP2e64InstAlias<V_SUBREV_CO_U32_e64, V_SUBREV_I32_e64_gfx6_gfx7>;
1409   def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
1414   def _e32_vi :
1420   def _e64_vi :
1426   def _e64_vi :
1441   def _sdwa_vi :
1448   def _sdwa_gfx9 :
1456   def _e32_vi :
1463   def _e64_vi :
1471     def _sdwa_vi :
1478     def _dpp_vi :
1490   def _e32_gfx9 :
1497   def _e64_gfx9 :
1505     def _sdwa_gfx9 :
1512     def _dpp_gfx9 :
1522   def _e32_gfx9 :
1527   def _e64_gfx9 :
1533     def _sdwa_gfx9 :
1538     def _dpp_gfx9 :
1551     def _dpp_vi :
1649 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
1650 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
1651 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
1652 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
1653 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
1679     def _e32_gfx90a :
1685     def _e64_gfx90a :
1698       def _dpp_gfx90a :
1714   def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;