scite/src/Embedded.properties

46 ext.lua.auto.reload=1
77 eol.auto=1
258 tacl tal txt2tags verilog vhdl visualprolog
267 filter.abaqus=ABAQUS input (inp)|$(file.patterns.abaqus)|
294 arguments=elset engineering inc input line material name nset pin tie type write generate field var…
1433 after.group: after.input: after.layout: after.program: after.receive.data: after.rewrite: after.ski…
1435 before.display: before.field: before.form: before.group: before.input: before.layout: before.new.ob…
1436 before.read: before.rewrite: before.write: before.zoom: check.input: declaration: domain.error: ini…
1437 on.display.total.line: on.entry: on.error: on.exit: on.input: read.view: ref.display: ref.input: se…
1443 group gt having hint hints if in include index inner input inrange integer is join label last le le…
1456 … after.delete: after.display: after.field: after.form: after.group: after.input: after.layout: aft…
1458 before.group: before.input: before.layout: before.print: before.read: before.rewrite: before.write:…
1459 init.group: on.choice: on.entry: on.exit: on.input: read.view: ref.display: ref.input: selection.fi…
1516 imagexhandle imageyhandle include input insert instr int joinnetgame joydown \
1672 option Some None ignore ref lnot succ pred parser
1676 option SOME NONE ignore ref \
1730 keywordclass.cil.main=abstract ansi assembly auto autochar beforefieldinit \
2082 … file file-control function function-id i-o i-o-control identification input input-output linkage …
2114 arithmetic attribute auto away-from-zero background-color bell binary-c-long binary-encoding blink …
2383 keywordclass.cpp=alignas alignof and and_eq asm audit auto axiom bitand bitor bool break \
2452 auto array bool break case char class complex ComplexInf ComplexNaN \
2515 id idempotent ignore iid_as iid_is immediatebind implicit_handle \
2903 auto none normal italic oblique small-caps bold bolder lighter \
3050 keywords.$(file.patterns.d)=abstract alias align asm assert auto \
3700 if image index input intensity \
4089 inkey inp input instr int integer is kill lbound lcase left len let lib line \
4328 head hr html i iframe img input ins isindex kbd label \
4969 call-with-input-file call-with-output-file call-with-values \
4980 close-input-port close-output-port complex? cond cons cos \
4981 current-input-port current-output-port \
4987 if imag-part inexact->exact inexact? input-port? integer->char integer? interaction-environment \
4993 odd? open-input-file open-output-file or output-port? \
4994 pair? peek-char input-port? output-port? positive? procedure? \
5006 with-input-from-file with-output-to-file write write-char \
5216 io.close io.flush io.input io.lines io.open \
5650     addto clip input interim let newinternal save setbounds \
6144 SW_SHOWNORMAL SYSTEM TEMPORARY auto colored false force hide ifnewer nevershow \
6212 heap iconfig image in inData index inode input int inter interdom interpreter \
7029 index input inputcancel inputdefault inputdialog join length messagebox mouse \
7729 index? info? inform input input? \
7776 index? info? input? integer? issue? length? lesser-or-equal? lesser? library? \
8194 verilog vhdl \
8197 list of all radix hex dec bin ignore illegal \
8451 identity if ignore immediate in indicator initialize initially \
8452 inner inout input insert int integer intersect interval \
8545 when where window with commit only regexp rlike rollback start \
8556 format formatted functions hold_ddltime idxproperties ignore index \
8561 read readonly rebuild recordreader recordwriter regexp reload rename repair \
8600 inner input in into is left matches not onschema or outer output \
8723 puts pwd re_syntax read regexp registry regsub rename \
8925 lexer.tex.auto.if=1
8957     ignorespaces immediate indent input inputlineno input \
9315 global gosub goto if imp implements in input integer is len let lib like load lock long \
9324 appactivate beep chdir chdrive close filecopy get input kill line unlock mkdir name \
9328 addhandler andalso ansi assembly auto catch cbool cbyte cchar cdate cdec char class \
9384 module verilog
9386 file.patterns.verilog=*.v;*.vh
9387 filter.verilog=Verilog (verilog)|$(file.patterns.verilog)|
9389 *filter.verilog=$(filter.verilog)
9391 lexer.$(file.patterns.verilog)=verilog
9393 *language.verilog=Verilog|v||
9395 word.chars.verilog=$(chars.alpha)$(chars.numeric)_`$#
9396 word.characters.$(file.patterns.verilog)=$(word.chars.verilog)
9398 calltip.verilog.word.characters=$(chars.alpha)$(chars.numeric)_$
9400 comment.block.verilog=//~
9401 comment.stream.start.verilog=/*
9402 comment.stream.end.verilog=*/
9403 comment.box.start.verilog=/*
9404 comment.box.middle.verilog= *
9405 comment.box.end.verilog= */
9407 fold.verilog.flags=0
9409 statement.lookback.$(file.patterns.verilog)=20
9410 statement.end.$(file.patterns.verilog)=10 ;
9411 block.start.$(file.patterns.verilog)=5 begin case casex casez
9412 block.end.$(file.patterns.verilog)=5 begin end endcase
9413 statement.indent.$(file.patterns.verilog)=5 always else for if while
9415 indent.maintain.$(file.patterns.verilog)=0
9417 preprocessor.symbol.$(file.patterns.verilog)=`
9418 preprocessor.start.$(file.patterns.verilog)=ifdef ifndef
9419 preprocessor.middle.$(file.patterns.verilog)=else
9420 preprocessor.end.$(file.patterns.verilog)=endif
9422 keywordclass.verilog= \
9431 if ifnone incdir include initial inout input instance integer \
9446 keywords.$(file.patterns.verilog)=$(keywordclass.verilog)
9448 keywords2.$(file.patterns.verilog)=
9449 keywords3.$(file.patterns.verilog)= \
9459 $incsave $input $itor \
9472 keywords4.$(file.patterns.verilog)=
9473 keywords5.$(file.patterns.verilog)= synopsys parallel_case infer_mux TODO
9479 lexer.$(file.patterns.systemverilog)=verilog
9507 ignore_bins illegal_bins import incdir include initial inout input inside \
9542 $history $hold $hypot $increment $incsave $info $input $isunbounded $isunknown \
9565 style.verilog.32=$(font.base)
9566 style.verilog.0=fore:#808080
9567 style.verilog.1=$(colour.code.comment.box),$(font.code.comment.box)
9568 style.verilog.2=$(colour.code.comment.line),$(font.code.comment.line)
9569 style.verilog.3=fore:#3F7F3F,$(font.code.comment.line),back:#E0F0FF,eolfilled
9570 style.verilog.4=$(colour.number)
9571 style.verilog.5=fore:#7f005f,bold
9572 style.verilog.6=$(colour.string),$(font.string.literal)
9573 style.verilog.7=fore:#007F7F
9574 style.verilog.8=fore:#804020
9575 style.verilog.9=$(colour.preproc)
9576 style.verilog.10=fore:#007070
9577 style.verilog.11=
9578 style.verilog.12=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
9579 style.verilog.19=fore:#2a00ff
9580 style.verilog.20=fore:#2A00FF
9581 style.verilog.21=fore:#7F0000
9582 style.verilog.22=fore:#00007F
9583 style.verilog.23=fore:#0000FF
9584 style.verilog.24=fore:#005032,bold
9586 lexer.verilog.portstyling=1
9587 lexer.verilog.allupperkeywords=1
9589 lexer.verilog.track.preprocessor=1
9590 lexer.verilog.update.preprocessor=1
9593 style.verilog.64=back:#E0E0E0,eolfilled
9594 style.verilog.65=back:#E0E0E0,eolfilled,fore:#808080,italics
9595 style.verilog.66=back:#E0E0E0,eolfilled,fore:#808080,italics
9596 style.verilog.67=back:#E0E0E0,eolfilled,fore:#808080,italics
9597 style.verilog.68=back:#E0E0E0,eolfilled,fore:#808080,italics
9598 style.verilog.69=back:#E0E0E0,eolfilled,fore:#808080,italics
9599 style.verilog.70=back:#E0E0E0,eolfilled,fore:#808080,italics
9600 style.verilog.71=back:#E0E0E0,eolfilled,fore:#808080,italics
9601 style.verilog.72=back:#E0E0E0,eolfilled,fore:#808080,italics
9602 style.verilog.73=back:#E0E0E0,eolfilled,fore:#808080,italics
9603 style.verilog.74=back:#E0E0E0,eolfilled,fore:#808080,italics
9604 style.verilog.75=back:#E0E0E0,eolfilled,fore:#808080,italics
9605 style.verilog.76=back:#E0E0E0,eolfilled,fore:#808080,italics
9606 style.verilog.83=back:#E0E0E0,eolfilled,fore:#808080,italics
9607 style.verilog.84=back:#E0E0E0,eolfilled,fore:#808080,italics
9608 style.verilog.85=back:#E0E0E0,eolfilled,fore:#808080,italics
9609 style.verilog.86=back:#E0E0E0,eolfilled,fore:#808080,italics
9610 style.verilog.87=back:#E0E0E0,eolfilled,fore:#808080,italics
9611 style.verilog.88=back:#E0E0E0,eolfilled,fore:#808080,italics
9613 braces.verilog.style=10