319 	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
321 	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);  in spl_dram_init_imx6qp_lpddr3()
323 	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);  in spl_dram_init_imx6qp_lpddr3()
324 	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);  in spl_dram_init_imx6qp_lpddr3()
331 	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);  in spl_dram_init_imx6qp_lpddr3()
332 	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);  in spl_dram_init_imx6qp_lpddr3()
335 	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);  in spl_dram_init_imx6qp_lpddr3()
337 	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);  in spl_dram_init_imx6qp_lpddr3()
339 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);  in spl_dram_init_imx6qp_lpddr3()
340 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);  in spl_dram_init_imx6qp_lpddr3()
341 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);  in spl_dram_init_imx6qp_lpddr3()
342 	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);  in spl_dram_init_imx6qp_lpddr3()
347 	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);  in spl_dram_init_imx6qp_lpddr3()
349 	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);  in spl_dram_init_imx6qp_lpddr3()
352 	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);  in spl_dram_init_imx6qp_lpddr3()
353 	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);  in spl_dram_init_imx6qp_lpddr3()
354 	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);  in spl_dram_init_imx6qp_lpddr3()
355 	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);  in spl_dram_init_imx6qp_lpddr3()
356 	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);  in spl_dram_init_imx6qp_lpddr3()
357 	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);  in spl_dram_init_imx6qp_lpddr3()
358 	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
359 	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);  in spl_dram_init_imx6qp_lpddr3()
360 	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);  in spl_dram_init_imx6qp_lpddr3()
361 	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);  in spl_dram_init_imx6qp_lpddr3()
362 	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);  in spl_dram_init_imx6qp_lpddr3()
363 	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);  in spl_dram_init_imx6qp_lpddr3()
364 	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);  in spl_dram_init_imx6qp_lpddr3()
372 	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
373 	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
374 	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
375 	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
376 	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()
377 	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);  in spl_dram_init_imx6qp_lpddr3()
378 	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);  in spl_dram_init_imx6qp_lpddr3()
380 	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);  in spl_dram_init_imx6qp_lpddr3()
381 	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);  in spl_dram_init_imx6qp_lpddr3()
382 	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);  in spl_dram_init_imx6qp_lpddr3()