target/openrisc/cpu.h

248 typedef struct CPUOpenRISCState {  struct
249     target_ulong shadow_gpr[16][32]; /* Shadow registers */
251     target_ulong pc;          /* Program counter */
252     target_ulong ppc;         /* Prev PC */
253     target_ulong jmp_pc;      /* Jump PC */
255     uint64_t mac;             /* Multiply registers MACHI:MACLO */
257     target_ulong epcr;        /* Exception PC register */
258     target_ulong eear;        /* Exception EA register */
260     target_ulong sr_f;        /* the SR_F bit, values 0, 1.  */
261     target_ulong sr_cy;       /* the SR_CY bit, values 0, 1.  */
262     target_long  sr_ov;       /* the SR_OV bit (in the sign bit only) */
263     uint32_t sr;              /* Supervisor register, without SR_{F,CY,OV} */
264     uint32_t esr;             /* Exception supervisor register */
265     uint32_t evbar;           /* Exception vector base address register */
266     uint32_t pmr;             /* Power Management Register */
267     uint32_t fpcsr;           /* Float register */
268     float_status fp_status;
270     target_ulong lock_addr;
271     target_ulong lock_value;
273     uint32_t dflag;           /* In delay slot (boolean) */
276     CPUOpenRISCTLBContext tlb;
300 } CPUOpenRISCState;  argument