target/ppc/cpu.h

962 struct CPUPPCState {  struct
968     target_ulong gpr[32];
970     target_ulong gprh[32];
972     target_ulong lr;
974     target_ulong ctr;
976     uint32_t crf[8];
979     target_ulong cfar;
982     target_ulong xer;
983     target_ulong so;
984     target_ulong ov;
985     target_ulong ca;
986     target_ulong ov32;
987     target_ulong ca32;
989     target_ulong reserve_addr;
991     target_ulong reserve_val;
992     target_ulong reserve_val2;
996     target_ulong msr;
998     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1001     float_status fp_status;
1003     target_ulong fpscr;
1006     target_ulong nip;
1009     uint64_t retxh;
1012     int access_type;
1018     ppc_slb_t slb[MAX_SLB_ENTRIES];
1022     target_ulong sr[32];
1024     uint32_t nb_BATs;
1025     target_ulong DBAT[2][8];
1026     target_ulong IBAT[2][8];
1028     int32_t nb_tlb;      /* Total number of TLB                              */
1029     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1030     int nb_ways;     /* Number of ways in the TLB set                        */
1031     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1032     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1033     int nb_pids;     /* Number of available PID registers                    */
1034     int tlb_type;    /* Type of TLB we're dealing with                       */
1035     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1037     target_ulong pb[4];
1038     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1039     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1040     uint32_t tlb_need_flush; /* Delayed flush needed */
1047     target_ulong spr[1024];
1048     ppc_spr_t spr_cb[1024];
1050     uint32_t vscr;
1052     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1056     uint64_t spe_acc;
1057     uint32_t spe_fscr;
1062     float_status vec_status;
1066     ppc_tb_t *tb_env;
1068     ppc_dcr_t *dcr_env;
1070     int dcache_line_size;
1071     int icache_line_size;
1075     target_ulong msr_mask;
1076     powerpc_mmu_t mmu_model;
1077     powerpc_excp_t excp_model;
1078     powerpc_input_t bus_model;
1079     int bfd_mach;
1080     uint32_t flags;
1081     uint64_t insns_flags;
1082     uint64_t insns_flags2;
1084     ppc_slb_t vrma_slb;
1085     target_ulong rmls;
1088     int error_code;
1089     uint32_t pending_interrupts;
1095     uint32_t irq_input_state;
1096     void **irq_inputs;
1098     target_ulong excp_vectors[POWERPC_EXCP_NB];
1099     target_ulong excp_prefix;
1100     target_ulong ivor_mask;
1101     target_ulong ivpr_mask;
1102     target_ulong hreset_vector;
1103     hwaddr mpic_iack;
1127     int (*check_pow)(CPUPPCState *env);  argument
1130     void *load_info;    /* Holds boot loading state.  */
1143     uint8_t fit_period[4];
1144     uint8_t wdt_period[4];
1147     target_ulong tm_gpr[32];
1148     ppc_avr_t tm_vsr[64];
1149     uint64_t tm_cr;
1150     uint64_t tm_lr;
1151     uint64_t tm_ctr;
1152     uint64_t tm_fpscr;
1153     uint64_t tm_amr;
1154     uint64_t tm_ppr;
1155     uint64_t tm_vrsave;
1156     uint32_t tm_vscr;
1157     uint64_t tm_dscr;
1158     uint64_t tm_tar;