36 	struct vxge_hw_vpath_reg *vp_reg;  in vxge_hw_vpath_intr_enable()  local
44 	vp_reg = vpath->vp_reg;  in vxge_hw_vpath_intr_enable()
46 	writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);  in vxge_hw_vpath_intr_enable()
49 				&vp_reg->general_errors_reg);  in vxge_hw_vpath_intr_enable()
52 				&vp_reg->pci_config_errors_reg);  in vxge_hw_vpath_intr_enable()
55 				&vp_reg->mrpcim_to_vpath_alarm_reg);  in vxge_hw_vpath_intr_enable()
58 				&vp_reg->srpcim_to_vpath_alarm_reg);  in vxge_hw_vpath_intr_enable()
61 				&vp_reg->vpath_ppif_int_status);  in vxge_hw_vpath_intr_enable()
64 				&vp_reg->srpcim_msg_to_vpath_reg);  in vxge_hw_vpath_intr_enable()
67 				&vp_reg->vpath_pcipif_int_status);  in vxge_hw_vpath_intr_enable()
70 				&vp_reg->prc_alarm_reg);  in vxge_hw_vpath_intr_enable()
73 				&vp_reg->wrdma_alarm_status);  in vxge_hw_vpath_intr_enable()
76 				&vp_reg->asic_ntwk_vp_err_reg);  in vxge_hw_vpath_intr_enable()
79 				&vp_reg->xgmac_vp_int_status);  in vxge_hw_vpath_intr_enable()
81 	readq(&vp_reg->vpath_general_int_status);  in vxge_hw_vpath_intr_enable()
85 				&vp_reg->vpath_pcipif_int_mask);  in vxge_hw_vpath_intr_enable()
88 				&vp_reg->srpcim_msg_to_vpath_mask);  in vxge_hw_vpath_intr_enable()
91 				&vp_reg->srpcim_to_vpath_alarm_mask);  in vxge_hw_vpath_intr_enable()
94 				&vp_reg->mrpcim_to_vpath_alarm_mask);  in vxge_hw_vpath_intr_enable()
97 				&vp_reg->pci_config_errors_mask);  in vxge_hw_vpath_intr_enable()
104 		&vp_reg->general_errors_mask);  in vxge_hw_vpath_intr_enable()
113 		&vp_reg->kdfcctl_errors_mask);  in vxge_hw_vpath_intr_enable()
115 	__vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);  in vxge_hw_vpath_intr_enable()
119 		&vp_reg->prc_alarm_mask);  in vxge_hw_vpath_intr_enable()
121 	__vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);  in vxge_hw_vpath_intr_enable()
122 	__vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);  in vxge_hw_vpath_intr_enable()
126 				&vp_reg->asic_ntwk_vp_err_mask);  in vxge_hw_vpath_intr_enable()
131 			0, 32), &vp_reg->asic_ntwk_vp_err_mask);  in vxge_hw_vpath_intr_enable()
133 	__vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_general_int_mask);  in vxge_hw_vpath_intr_enable()
152 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in vxge_hw_vpath_intr_disable()  local
158 	vp_reg = vpath->vp_reg;  in vxge_hw_vpath_intr_disable()
161 			&vp_reg->vpath_general_int_mask);  in vxge_hw_vpath_intr_disable()
163 	writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);  in vxge_hw_vpath_intr_disable()
166 			&vp_reg->general_errors_mask);  in vxge_hw_vpath_intr_disable()
169 			&vp_reg->pci_config_errors_mask);  in vxge_hw_vpath_intr_disable()
172 			&vp_reg->mrpcim_to_vpath_alarm_mask);  in vxge_hw_vpath_intr_disable()
175 			&vp_reg->srpcim_to_vpath_alarm_mask);  in vxge_hw_vpath_intr_disable()
178 			&vp_reg->vpath_ppif_int_mask);  in vxge_hw_vpath_intr_disable()
181 			&vp_reg->srpcim_msg_to_vpath_mask);  in vxge_hw_vpath_intr_disable()
184 			&vp_reg->vpath_pcipif_int_mask);  in vxge_hw_vpath_intr_disable()
187 			&vp_reg->wrdma_alarm_mask);  in vxge_hw_vpath_intr_disable()
190 			&vp_reg->prc_alarm_mask);  in vxge_hw_vpath_intr_disable()
193 			&vp_reg->xgmac_vp_int_mask);  in vxge_hw_vpath_intr_disable()
196 			&vp_reg->asic_ntwk_vp_err_mask);  in vxge_hw_vpath_intr_disable()
424 	struct vxge_hw_vpath_reg *vp_reg;  in __vxge_hw_vpath_alarm_process()  local
427 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_alarm_process()
428 	alarm_status = readq(&vp_reg->vpath_general_int_status);  in __vxge_hw_vpath_alarm_process()
452 		val64 = readq(&vp_reg->xgmac_vp_int_status);  in __vxge_hw_vpath_alarm_process()
457 			val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);  in __vxge_hw_vpath_alarm_process()
469 					&vp_reg->asic_ntwk_vp_err_mask);  in __vxge_hw_vpath_alarm_process()
486 					&vp_reg->asic_ntwk_vp_err_mask);  in __vxge_hw_vpath_alarm_process()
494 				&vp_reg->asic_ntwk_vp_err_reg);  in __vxge_hw_vpath_alarm_process()
628 			&ring->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_doorbell_rx()