98 	u32 confr;  in zynq_spi_init_hw()  local
101 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_init_hw()
102 	writel(~confr, &regs->enr);  in zynq_spi_init_hw()
116 	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |  in zynq_spi_init_hw()
118 	confr &= ~ZYNQ_SPI_CR_MSA_MASK;  in zynq_spi_init_hw()
119 	writel(confr, &regs->cr);  in zynq_spi_init_hw()
200 	u32 confr;  in zynq_spi_release_bus()  local
202 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_release_bus()
203 	writel(~confr, &regs->enr);  in zynq_spi_release_bus()
279 	uint32_t confr;  in zynq_spi_set_speed()  local
286 	confr = readl(&regs->cr);  in zynq_spi_set_speed()
297 	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;  in zynq_spi_set_speed()
298 	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);  in zynq_spi_set_speed()
300 	writel(confr, &regs->cr);  in zynq_spi_set_speed()
313 	uint32_t confr;  in zynq_spi_set_mode()  local
316 	confr = readl(&regs->cr);  in zynq_spi_set_mode()
317 	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);  in zynq_spi_set_mode()
320 		confr |= ZYNQ_SPI_CR_CPHA_MASK;  in zynq_spi_set_mode()
322 		confr |= ZYNQ_SPI_CR_CPOL_MASK;  in zynq_spi_set_mode()
324 	writel(confr, &regs->cr);  in zynq_spi_set_mode()