Lines Matching refs:vec4_instruction

157    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
163 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
178 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
186 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
187 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
188 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src…
210 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
212 vec4_instruction *IF(src_reg src0, src_reg src1,
214 vec4_instruction *IF(enum brw_predicate predicate);
234 vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
248 vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
280 vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying, int comp);
287 src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
289 void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
293 void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
295 void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
304 vec4_instruction *before_inst);
306 vec4_instruction *inst, src_reg src);
324 vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
328 vec4_instruction *ref = NULL);
370 virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;