570 gp100_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index,  in gp100_cp_launch_desc_set_cb()  argument
578    NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);  in gp100_cp_launch_desc_set_cb()
579    NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);  in gp100_cp_launch_desc_set_cb()
580    NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index,  in gp100_cp_launch_desc_set_cb()
582    NVC0C0_QMDV02_01_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);  in gp100_cp_launch_desc_set_cb()
586 nve4_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, struct nouveau_bo *bo,  in nve4_cp_launch_desc_set_cb()  argument
594    NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);  in nve4_cp_launch_desc_set_cb()
595    NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);  in nve4_cp_launch_desc_set_cb()
596    NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_SIZE, index, size);  in nve4_cp_launch_desc_set_cb()
597    NVA0C0_QMDV00_06_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);  in nve4_cp_launch_desc_set_cb()
625 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,  in nve4_compute_setup_launch_desc()  argument
631    NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_HEADER_CACHE, TRUE);  in nve4_compute_setup_launch_desc()
632    NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_SAMPLER_CACHE, TRUE);  in nve4_compute_setup_launch_desc()
633    NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_DATA_CACHE, TRUE);  in nve4_compute_setup_launch_desc()
634    NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_SHADER_DATA_CACHE, TRUE);  in nve4_compute_setup_launch_desc()
635    NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_SHADER_CONSTANT_CACHE, TRUE);  in nve4_compute_setup_launch_desc()
636    NVA0C0_QMDV00_06_DEF_SET(qmd, RELEASE_MEMBAR_TYPE, FE_SYSMEMBAR);  in nve4_compute_setup_launch_desc()
637    NVA0C0_QMDV00_06_DEF_SET(qmd, CWD_MEMBAR_TYPE, L1_SYSMEMBAR);  in nve4_compute_setup_launch_desc()
638    NVA0C0_QMDV00_06_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);  in nve4_compute_setup_launch_desc()
639    NVA0C0_QMDV00_06_VAL_SET(qmd, SASS_VERSION, 0x30);  in nve4_compute_setup_launch_desc()
641    NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);  in nve4_compute_setup_launch_desc()
643    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);  in nve4_compute_setup_launch_desc()
644    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);  in nve4_compute_setup_launch_desc()
645    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_DEPTH, info->grid[2]);  in nve4_compute_setup_launch_desc()
646    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION0, info->block[0]);  in nve4_compute_setup_launch_desc()
647    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION1, info->block[1]);  in nve4_compute_setup_launch_desc()
648    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION2, info->block[2]);  in nve4_compute_setup_launch_desc()
650    NVA0C0_QMDV00_06_VAL_SET(qmd, SHARED_MEMORY_SIZE,  in nve4_compute_setup_launch_desc()
652    NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,  in nve4_compute_setup_launch_desc()
655    NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);  in nve4_compute_setup_launch_desc()
656    NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, 0x800);  in nve4_compute_setup_launch_desc()
659       NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,  in nve4_compute_setup_launch_desc()
663       NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,  in nve4_compute_setup_launch_desc()
666       NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,  in nve4_compute_setup_launch_desc()
669    NVA0C0_QMDV00_06_VAL_SET(qmd, REGISTER_COUNT, cp->num_gprs);  in nve4_compute_setup_launch_desc()
670    NVA0C0_QMDV00_06_VAL_SET(qmd, BARRIER_COUNT, cp->num_barriers);  in nve4_compute_setup_launch_desc()
676       nve4_cp_launch_desc_set_cb(qmd, 0, screen->uniform_bo,  in nve4_compute_setup_launch_desc()
683    nve4_cp_launch_desc_set_cb(qmd, 7, screen->uniform_bo,  in nve4_compute_setup_launch_desc()
686    nve4_compute_setup_buf_cb(nvc0, false, qmd);  in nve4_compute_setup_launch_desc()
690 gp100_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,  in gp100_compute_setup_launch_desc()  argument
696    NVC0C0_QMDV02_01_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);  in gp100_compute_setup_launch_desc()
697    NVC0C0_QMDV02_01_DEF_SET(qmd, RELEASE_MEMBAR_TYPE, FE_SYSMEMBAR);  in gp100_compute_setup_launch_desc()
698    NVC0C0_QMDV02_01_DEF_SET(qmd, CWD_MEMBAR_TYPE, L1_SYSMEMBAR);  in gp100_compute_setup_launch_desc()
699    NVC0C0_QMDV02_01_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);  in gp100_compute_setup_launch_desc()
701    NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);  in gp100_compute_setup_launch_desc()
703    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);  in gp100_compute_setup_launch_desc()
704    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);  in gp100_compute_setup_launch_desc()
705    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_DEPTH, info->grid[2]);  in gp100_compute_setup_launch_desc()
706    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_THREAD_DIMENSION0, info->block[0]);  in gp100_compute_setup_launch_desc()
707    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_THREAD_DIMENSION1, info->block[1]);  in gp100_compute_setup_launch_desc()
708    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_THREAD_DIMENSION2, info->block[2]);  in gp100_compute_setup_launch_desc()
710    NVC0C0_QMDV02_01_VAL_SET(qmd, SHARED_MEMORY_SIZE,  in gp100_compute_setup_launch_desc()
712    NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,  in gp100_compute_setup_launch_desc()
715    NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);  in gp100_compute_setup_launch_desc()
716    NVC0C0_QMDV02_01_VAL_SET(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, 0x800);  in gp100_compute_setup_launch_desc()
718    NVC0C0_QMDV02_01_VAL_SET(qmd, REGISTER_COUNT, cp->num_gprs);  in gp100_compute_setup_launch_desc()
719    NVC0C0_QMDV02_01_VAL_SET(qmd, BARRIER_COUNT, cp->num_barriers);  in gp100_compute_setup_launch_desc()
725       gp100_cp_launch_desc_set_cb(qmd, 0, screen->uniform_bo,  in gp100_compute_setup_launch_desc()
732    gp100_cp_launch_desc_set_cb(qmd, 7, screen->uniform_bo,  in gp100_compute_setup_launch_desc()
735    nve4_compute_setup_buf_cb(nvc0, true, qmd);  in gp100_compute_setup_launch_desc()
750 gv100_compute_setup_launch_desc(struct nvc0_context *nvc0, u32 *qmd,  in gv100_compute_setup_launch_desc()  argument
757    NVC3C0_QMDV02_02_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);  in gv100_compute_setup_launch_desc()
758    NVC3C0_QMDV02_02_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);  in gv100_compute_setup_launch_desc()
759    NVC3C0_QMDV02_02_DEF_SET(qmd, SAMPLER_INDEX, INDEPENDENTLY);  in gv100_compute_setup_launch_desc()
760    NVC3C0_QMDV02_02_VAL_SET(qmd, SHARED_MEMORY_SIZE,  in gv100_compute_setup_launch_desc()
762    NVC3C0_QMDV02_02_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,  in gv100_compute_setup_launch_desc()
765    NVC3C0_QMDV02_02_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);  in gv100_compute_setup_launch_desc()
766    NVC3C0_QMDV02_02_VAL_SET(qmd, MIN_SM_CONFIG_SHARED_MEM_SIZE,  in gv100_compute_setup_launch_desc()
768    NVC3C0_QMDV02_02_VAL_SET(qmd, MAX_SM_CONFIG_SHARED_MEM_SIZE,  in gv100_compute_setup_launch_desc()
770    NVC3C0_QMDV02_02_VAL_SET(qmd, QMD_VERSION, 2);  in gv100_compute_setup_launch_desc()
771    NVC3C0_QMDV02_02_VAL_SET(qmd, QMD_MAJOR_VERSION, 2);  in gv100_compute_setup_launch_desc()
772    NVC3C0_QMDV02_02_VAL_SET(qmd, TARGET_SM_CONFIG_SHARED_MEM_SIZE,  in gv100_compute_setup_launch_desc()
775    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);  in gv100_compute_setup_launch_desc()
776    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);  in gv100_compute_setup_launch_desc()
777    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_RASTER_DEPTH, info->grid[2]);  in gv100_compute_setup_launch_desc()
778    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_THREAD_DIMENSION0, info->block[0]);  in gv100_compute_setup_launch_desc()
779    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_THREAD_DIMENSION1, info->block[1]);  in gv100_compute_setup_launch_desc()
780    NVC3C0_QMDV02_02_VAL_SET(qmd, CTA_THREAD_DIMENSION2, info->block[2]);  in gv100_compute_setup_launch_desc()
781    NVC3C0_QMDV02_02_VAL_SET(qmd, REGISTER_COUNT_V, cp->num_gprs);  in gv100_compute_setup_launch_desc()
782    NVC3C0_QMDV02_02_VAL_SET(qmd, BARRIER_COUNT, cp->num_barriers);  in gv100_compute_setup_launch_desc()
788       gp100_cp_launch_desc_set_cb(qmd, 0, screen->uniform_bo,  in gv100_compute_setup_launch_desc()
795    gp100_cp_launch_desc_set_cb(qmd, 7, screen->uniform_bo,  in gv100_compute_setup_launch_desc()
798    nve4_compute_setup_buf_cb(nvc0, true, qmd);  in gv100_compute_setup_launch_desc()
800    NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, entry & 0xffffffff);  in gv100_compute_setup_launch_desc()
801    NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, entry >> 32);  in gv100_compute_setup_launch_desc()