config/frv/frv.md

5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
12 ;; GCC is distributed in the hope that it will be useful,
100 ;; Attribute is "yes" for branches and jumps that span too great a distance
119 ;; media, branch and control.  Each group is associated with a separate set
127 ;; to I0.  As well as these processor-specific restrictions, there is a
131 ;; Sometimes the only way to honor these restrictions is by adding nops
133 ;; ACC4-7 can only issue to M1 or M3.  It is therefore only possible to
147 ;; instructions in the same packet, even if the write is listed earlier
169 ;;	  worst case, assuming the predicate is true.  However, if we have
173 ;;	  in order to optimize the case when the predicate is false.
177 ;;	  Since (2) inserts nops, it is possible that some branches
182 ;; question that the DFAs are supposed to answer is simply: can these
218 ;; above, where the rule is not as simple as "any unit between 0 and X".
238 ;;	 (c) If this is the control or branch group, goto (i)
242 ;;	     claims unit X when S[X] is added.  Let D be the DFA state
245 ;;	 (e) If L is the length of S, goto (i)
253 ;;	     X + L when each S''[X] is added.  If so, set S to the
258 ;;	 (i) S is now the sorted sequence for this group, meaning that S[X]
261 ;; The sequence calculated by (b) is trivially correct for control
262 ;; instructions since they can't be packed.  It is also correct for branch
264 ;; floating-point/media instructions, the sequence calculated by (b) is
265 ;; often the correct answer; the rest of the algorithm is optimized for
266 ;; the case in which it is correct.
269 ;; (d) would not be needed.  It is mainly there to cope with the fr550
276 ;; Step (g) is the main one for integer and float/media instructions.
277 ;; The first permutation it tries is S' itself (because, as noted above,
278 ;; the sequence calculated by (b) is often correct).  If S' doesn't work,
283 ;; The algorithm is theoretically exponential in the number of instructions
285 ;; (b) is acceptable.  In practice, the algorithm completes quickly even
413 ;; Media insns.  Conflict table is as follows:
516 ;; than indicated.  The penalty given is for instructions with write-after-
542 ;; 3 is the worst case (write-after-write hazard).
569 ;; 20 is for a write-after-write hazard.
580 ;; 4 is for a write-after-write hazard.
591 ;; 4 is for a write-after-write hazard.
602 ;; 3 is for a write-after-write hazard.
613 ;; 3 is for a write-after-write hazard.
686 ;; is needed later.
742 ;; There is no difference between M-1 and M-3 as far as issue
765 ;; as scheduling is concerned.  The inputs and outputs are FPRs.
887 ;; This means that, as far as frv_reorder_packet is concerned,
941 ;; is to fix the reservation for the fnop insn so that it does not have the
987 ;; In addition -- and this is the awkward bit! -- instructions that
1144 ;; delay slots, if any, on a target machine.  An instruction is said to require
1148 ;; instruction before the branch or call is performed.
1153 ;; branch is true and instructions that annul if the branch is false are
1157 ;; determining whether an instruction needs a delay slot is dependent only
1162 ;; The requirement of an insn needing one or more delay slots is indicated via
1170 ;; TEST is an attribute test that indicates whether this `define_delay' applies
1171 ;; to a particular insn.  If so, the number of required delay slots is
1174 ;; ANNUL-TRUE-N is an attribute test that specifies which insns may be annulled
1175 ;; if the branch is true.  Similarly, ANNUL-FALSE-N specifies which insns in
1176 ;; the delay slot may be annulled if the branch is false.  If annulling is not
1192 ;; valid insn in the delay slot for the branch can be annulled if the branch is
1204 ;; Note - it is the backend's responsibility to fill any unfilled delay slots
1205 ;; at assembler generation time.  This is usually done by adding a special print
1256 ;; Also if there is more than one instruction, they can be separated by \\;
1257 ;; which is a space saving synonym for \\n\\t:
1284 ;; If operand 0 is a `subreg' with mode M of a register whose own mode is wider
1285 ;; than M, the effect of this instruction is to store the specified value in
1287 ;; of the register is undefined.
1289 ;; This class of patterns is special in several ways.  First of all, each of
1290 ;; these names *must* be defined, because there is no other way to copy a datum
1295 ;; temporary registers.  When it does so, one of the operands is a hard
1296 ;; register and the other is an operand that can need to be reloaded into a
1314 ;; use it as it stands.  If it is copied, it will not be replaced with a valid
1321 ;; if required) can be used to determine whether such special handling is
1330 ;; If a scratch register is required to move an object to or from memory, it
1331 ;; can be allocated using `gen_reg_rtx' prior to reload.  But this is
1342 ;; It is obligatory to support floating point `moveM' instructions
1350 ;; forgotten why this was so, and I don't know whether it is still true.
1435 ;; Note - it is best to only have one movsi pattern and to handle
1444 ;; constants into memory when the destination is a floating-point register.
1611      register operand 0 is the same as the second register of operand 1, we
1818      register operand 0 is the same as the second register of operand 1, we
1885 ;; Argument 0 is the destination
1886 ;; Argument 1 is the source
1887 ;; Argument 2 is the length
1888 ;; Argument 3 is the alignment
1905 ;; Argument 0 is the destination
1906 ;; Argument 1 is the length
1907 ;; Argument 2 is the byte value -- ignore any value but zero
1908 ;; Argument 3 is the alignment
1918   /* If value to set is not zero, use the library routine.  */
1930 ;; Operand 0 is a volatile reference to the memory that the function reads
1931 ;; or writes.  Operand 1 is the address being accessed, or zero if the
2081 ;; Reload CC_NZmode.  This is mostly the same as the CCmode and CC_UNSmode
2112 ;; flags don't matter.  The sequence is:
3379    mnot %1, %0"
3500 ;; The only requirement for a CC_NZmode GPR or memory value is that
3502 ;; The source operand is therefore a valid CC_NZmode value.
3574 ;; If a fixed condition code register is being used, (as opposed to, say,
3589 ;; In the above example the %B is a directive to frv_print_operand()
3983 ;; DImode in this case if the user is only interested in the lower 32-bits.  So
4321 ;;   TARGET_HARD_FLOAT, because an FPU is required to do the comparison.
4856 ;; Subroutine call instruction returning no value.  Operand 0 is the function
4857 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4858 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4861 ;; On most machines, operand 2 is not actually stored into the RTL pattern.  It
4862 ;; is supplied for the sake of some RISC machines which need to put this
4907 ;; hoisting function descriptor loads out of loops.  This is almost
4981 ;; sure LR is restored, and having LR here will set
5010 ;; Subroutine call instruction returning a value.  Operand 0 is the hard
5011 ;; register in which the value is returned.  There are three more operands, the
5188 ;; epilogue.  The addition is done in parallel with an (unspec_volatile),
5206 ;; instruction it emits.  Since the main branch-shortening interface is
5208 ;; lengths.  Here we pretend that the far jump is 8 rather than 4 bytes
5247 ;; Instruction to jump to a variable address.  This is a low-level capability
5248 ;; which can be used to implement a dispatch table when there is no `casesi'
5254 ;; `CASE_VECTOR_PC_RELATIVE' is defined then the first operand is an offset
5255 ;; which counts from the address of the table; otherwise, it is an absolute
5258 ;; The `tablejump' insn is always the last insn before the jump table it uses.
5281 ;; operand 0 is the index
5282 ;; operand 1 is the lower bound
5283 ;; operand 2 is the range of indices (highest - lowest + 1)
5284 ;; operand 3 is the label that precedes the table itself
5285 ;; operand 4 is the fall through label
5315   /* If low bound is 0, we don't have to subtract it.  */
5331      check that the original index expression value is both greater than
5364 ;; prologue.  Using a prologue insn is favored compared to putting all of the
5379 ;; epilogue.  Using an epilogue insn is favored compared to putting all of the
5455 ;; point.  Note, type unknown is used to make sure the VLIW instructions are
5617 (define_insn "mnot"
5621   "mnot %1, %0"
6904 ;; What is the class of the insn ???
6914 ;; What is the class of the insn ???
7663 ;; We have to expand this like a libcall (it sort of actually is)