Lines Matching refs:MM0
303 #define ASM_SWAP16_2_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
310 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
312 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
313 psrlw $8, "MM0" # MM0: - 7 - 5 - 3 - 1 \n\
315 por "MM1", "MM0" # MM0: 6 7 4 5 2 3 0 1 \n\
316 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
322 #define ASM_SWAP32_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
329 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
331 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
332 psrld $16, "MM0" # MM0: - - 7 6 - - 3 2 \n\
334 por "MM1", "MM0" # MM0: 5 4 7 6 1 0 3 2 \n\
335 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
341 #define ASM_SWAP32_02_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
348 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
350 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
351 "movq" "MM0", "MM2" # MM2: 7 6 5 4 3 2 1 0 \n\
356 pand 160("EDX"), "MM0" # MM0: 7 - 5 - 3 - 1 - \n\
357 por "MM1", "MM0" # MM0: 7 4 5 - 3 0 1 - \n\
358 por "MM2", "MM0" # MM0: 7 4 5 6 3 0 1 2 \n\
359 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
366 #define ASM_SWAP32_13_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
373 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
375 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
376 "movq" "MM0", "MM2" # MM2: 7 6 5 4 3 2 1 0 \n\
381 pand 80("EDX"), "MM0" # MM0: - 6 - 4 - 2 - 0 \n\
382 por "MM1", "MM0" # MM0: 5 6 - 4 1 2 - 0 \n\
383 por "MM2", "MM0" # MM0: 5 6 7 4 1 2 3 0 \n\
384 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
391 #define ASM_REV32_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
398 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
400 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
401 "movq" "MM0", "MM2" # MM2: 7 6 5 4 3 2 1 0 \n\
402 "movq" "MM0", "MM3" # MM3: 7 6 5 4 3 2 1 0 \n\
403 psrld $24, "MM0" # MM0: - - - 7 - - - 3 \n\
409 por "MM1", "MM0" # MM0: - - 6 7 - - 2 3 \n\
410 por "MM2", "MM0" # MM0: - 5 6 7 - 1 2 3 \n\
411 por "MM3", "MM0" # MM0: 4 5 6 7 0 1 2 3 \n\
412 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
419 #define ASM_ROL32_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
426 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
428 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
429 pslld $8, "MM0" # MM0: 6 5 4 - 2 1 0 - \n\
431 por "MM1", "MM0" # MM0: 6 5 4 7 2 1 0 3 \n\
432 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \
438 #define ASM_ROR32_SIMD(size,regsize,ldq,movq,stq,sfence,MM0,MM1,MM2,MM3,MM4,MM5,MM6,MM7) \ argument
445 ldq" -("#regsize"/8)("ESI","ECX",4), "MM0" \n\
447 "movq" "MM0", "MM1" # MM1: 7 6 5 4 3 2 1 0 \n\
448 psrld $8, "MM0" # MM0: - 7 6 5 - 3 2 1 \n\
450 por "MM1", "MM0" # MM0: 4 7 6 5 0 3 2 1 \n\
451 "stq" "MM0", -("#regsize"/8)("EDI","ECX",4)", \