18 	switch (sw->tmu.rate) {  in tb_switch_tmu_mode_name()
26 		if (sw->tmu.unidirectional)  in tb_switch_tmu_mode_name()
46 			 sw->tmu.cap + TMU_RTR_CS_0, 1);  in tb_switch_tmu_ucap_supported()
59 			 sw->tmu.cap + TMU_RTR_CS_3, 1);  in tb_switch_tmu_rate_read()
73 			 sw->tmu.cap + TMU_RTR_CS_3, 1);  in tb_switch_tmu_rate_write()
81 			   sw->tmu.cap + TMU_RTR_CS_3, 1);  in tb_switch_tmu_rate_write()
106 	if (!port->sw->tmu.has_ucap)  in tb_port_tmu_set_unidirectional()
137 			 sw->tmu.cap + TMU_RTR_CS_0, 1);  in tb_switch_tmu_set_time_disruption()
147 			   sw->tmu.cap + TMU_RTR_CS_0, 1);  in tb_switch_tmu_set_time_disruption()
168 		sw->tmu.cap = ret;  in tb_switch_tmu_init()
182 	sw->tmu.rate = ret;  in tb_switch_tmu_init()
184 	sw->tmu.has_ucap = tb_switch_tmu_ucap_supported(sw);  in tb_switch_tmu_init()
185 	if (sw->tmu.has_ucap) {  in tb_switch_tmu_init()
191 			sw->tmu.unidirectional =  in tb_switch_tmu_init()
195 		sw->tmu.unidirectional = false;  in tb_switch_tmu_init()
223 	if (!root_switch->tmu.cap)  in tb_switch_tmu_post_time()
227 			 root_switch->tmu.cap + TMU_RTR_CS_1,  in tb_switch_tmu_post_time()
248 	post_local_time_offset = sw->tmu.cap + TMU_RTR_CS_22;  in tb_switch_tmu_post_time()
249 	post_time_offset = sw->tmu.cap + TMU_RTR_CS_24;  in tb_switch_tmu_post_time()
306 	if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF)  in tb_switch_tmu_disable()
309 	if (sw->tmu.unidirectional) {  in tb_switch_tmu_disable()
325 	sw->tmu.unidirectional = false;  in tb_switch_tmu_disable()
326 	sw->tmu.rate = TB_SWITCH_TMU_RATE_OFF;  in tb_switch_tmu_disable()
354 	if (tb_route(sw) && sw->tmu.unidirectional) {  in tb_switch_tmu_enable()
378 	sw->tmu.unidirectional = false;  in tb_switch_tmu_enable()
379 	sw->tmu.rate = TB_SWITCH_TMU_RATE_HIFI;  in tb_switch_tmu_enable()