Lines Matching refs:ah
32 static int ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
37 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
54 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
57 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
63 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
68 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
73 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
79 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
83 static int ar9002_hw_per_calibration(struct ath_hw *ah, in ar9002_hw_per_calibration() argument
88 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9002_hw_per_calibration()
92 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
95 currCal->calData->calCollect(ah); in ar9002_hw_per_calibration()
96 ah->cal_samples++; in ar9002_hw_per_calibration()
98 if (ah->cal_samples >= in ar9002_hw_per_calibration()
106 currCal->calData->calPostProc(ah, numChains); in ar9002_hw_per_calibration()
111 ar9002_hw_setup_calibration(ah, currCal); in ar9002_hw_per_calibration()
115 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_per_calibration()
121 static void ar9002_hw_iqcal_collect(struct ath_hw *ah) in ar9002_hw_iqcal_collect() argument
126 ah->totalPowerMeasI[i] += in ar9002_hw_iqcal_collect()
127 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
128 ah->totalPowerMeasQ[i] += in ar9002_hw_iqcal_collect()
129 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
130 ah->totalIqCorrMeas[i] += in ar9002_hw_iqcal_collect()
131 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
134 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9002_hw_iqcal_collect()
135 ah->totalPowerMeasQ[i], in ar9002_hw_iqcal_collect()
136 ah->totalIqCorrMeas[i]); in ar9002_hw_iqcal_collect()
140 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) in ar9002_hw_adc_gaincal_collect() argument
145 ah->totalAdcIOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
146 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
147 ah->totalAdcIEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
148 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
149 ah->totalAdcQOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
151 ah->totalAdcQEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
156 ah->cal_samples, i, in ar9002_hw_adc_gaincal_collect()
157 ah->totalAdcIOddPhase[i], in ar9002_hw_adc_gaincal_collect()
158 ah->totalAdcIEvenPhase[i], in ar9002_hw_adc_gaincal_collect()
159 ah->totalAdcQOddPhase[i], in ar9002_hw_adc_gaincal_collect()
160 ah->totalAdcQEvenPhase[i]); in ar9002_hw_adc_gaincal_collect()
164 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) in ar9002_hw_adc_dccal_collect() argument
169 ah->totalAdcDcOffsetIOddPhase[i] += in ar9002_hw_adc_dccal_collect()
170 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
171 ah->totalAdcDcOffsetIEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
172 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
173 ah->totalAdcDcOffsetQOddPhase[i] += in ar9002_hw_adc_dccal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_dccal_collect()
175 ah->totalAdcDcOffsetQEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_dccal_collect()
180 ah->cal_samples, i, in ar9002_hw_adc_dccal_collect()
181 ah->totalAdcDcOffsetIOddPhase[i], in ar9002_hw_adc_dccal_collect()
182 ah->totalAdcDcOffsetIEvenPhase[i], in ar9002_hw_adc_dccal_collect()
183 ah->totalAdcDcOffsetQOddPhase[i], in ar9002_hw_adc_dccal_collect()
184 ah->totalAdcDcOffsetQEvenPhase[i]); in ar9002_hw_adc_dccal_collect()
188 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_iqcalibrate() argument
196 powerMeasI = ah->totalPowerMeasI[i]; in ar9002_hw_iqcalibrate()
197 powerMeasQ = ah->totalPowerMeasQ[i]; in ar9002_hw_iqcalibrate()
198 iqCorrMeas = ah->totalIqCorrMeas[i]; in ar9002_hw_iqcalibrate()
206 i, ah->totalIqCorrMeas[i]); in ar9002_hw_iqcalibrate()
249 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
252 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
261 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
265 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_gaincal_calibrate() argument
271 iOddMeasOffset = ah->totalAdcIOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
272 iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
273 qOddMeasOffset = ah->totalAdcQOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
274 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
307 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_gaincal_calibrate()
310 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
317 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
318 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_gaincal_calibrate()
322 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_dccal_calibrate() argument
327 ah->cal_list_curr->calData; in ar9002_hw_adc_dccal_calibrate()
332 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
333 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
334 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
335 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
365 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_dccal_calibrate()
368 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
374 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
375 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_dccal_calibrate()
379 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah) in ar9287_hw_olc_temp_compensation() argument
384 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9287_hw_olc_temp_compensation()
387 if (ah->initPDADC == 0 || currPDADC == 0) { in ar9287_hw_olc_temp_compensation()
395 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); in ar9287_hw_olc_temp_compensation()
400 delta = ((currPDADC - ah->initPDADC)*4) / slope; in ar9287_hw_olc_temp_compensation()
402 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
404 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
409 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah) in ar9280_hw_olc_temp_compensation() argument
414 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9280_hw_olc_temp_compensation()
417 if (ah->initPDADC == 0 || currPDADC == 0) in ar9280_hw_olc_temp_compensation()
420 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) in ar9280_hw_olc_temp_compensation()
421 delta = (currPDADC - ah->initPDADC + 4) / 8; in ar9280_hw_olc_temp_compensation()
423 delta = (currPDADC - ah->initPDADC + 5) / 10; in ar9280_hw_olc_temp_compensation()
425 if (delta != ah->PDADCdelta) { in ar9280_hw_olc_temp_compensation()
426 ah->PDADCdelta = delta; in ar9280_hw_olc_temp_compensation()
428 regval = ah->originalGain[i] - delta; in ar9280_hw_olc_temp_compensation()
432 REG_RMW_FIELD(ah, in ar9280_hw_olc_temp_compensation()
439 static void ar9271_hw_pa_cal(struct ath_hw *ah, int is_reset) in ar9271_hw_pa_cal() argument
455 regList[i][1] = REG_READ(ah, regList[i][0]); in ar9271_hw_pa_cal()
457 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
459 REG_WRITE(ah, 0x7834, regVal); in ar9271_hw_pa_cal()
460 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
462 REG_WRITE(ah, 0x9808, regVal); in ar9271_hw_pa_cal()
465 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); in ar9271_hw_pa_cal()
467 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); in ar9271_hw_pa_cal()
469 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); in ar9271_hw_pa_cal()
471 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); in ar9271_hw_pa_cal()
473 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); in ar9271_hw_pa_cal()
475 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); in ar9271_hw_pa_cal()
477 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); in ar9271_hw_pa_cal()
479 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); in ar9271_hw_pa_cal()
481 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); in ar9271_hw_pa_cal()
483 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); in ar9271_hw_pa_cal()
485 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9271_hw_pa_cal()
490 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9271_hw_pa_cal()
492 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff); in ar9271_hw_pa_cal()
498 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
500 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); in ar9271_hw_pa_cal()
504 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
506 REG_WRITE(ah, 0x7834, regVal); in ar9271_hw_pa_cal()
510 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9) in ar9271_hw_pa_cal()
512 REG_WRITE(ah, 0x7834, regVal); in ar9271_hw_pa_cal()
518 if ((!is_reset) && ((unsigned int)ah->pacal_info.prev_offset == regVal)) { in ar9271_hw_pa_cal()
519 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9271_hw_pa_cal()
520 ah->pacal_info.max_skipcount = in ar9271_hw_pa_cal()
521 2 * ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
522 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
524 ah->pacal_info.max_skipcount = 1; in ar9271_hw_pa_cal()
525 ah->pacal_info.skipcount = 0; in ar9271_hw_pa_cal()
526 ah->pacal_info.prev_offset = regVal; in ar9271_hw_pa_cal()
529 ENABLE_REGWRITE_BUFFER(ah); in ar9271_hw_pa_cal()
531 regVal = REG_READ(ah, 0x7834); in ar9271_hw_pa_cal()
533 REG_WRITE(ah, 0x7834, regVal); in ar9271_hw_pa_cal()
534 regVal = REG_READ(ah, 0x9808); in ar9271_hw_pa_cal()
536 REG_WRITE(ah, 0x9808, regVal); in ar9271_hw_pa_cal()
539 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9271_hw_pa_cal()
541 REGWRITE_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
544 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, int is_reset) in ar9285_hw_pa_cal() argument
563 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == in ar9285_hw_pa_cal()
568 regList[i][1] = REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
570 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
572 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
573 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
575 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
577 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); in ar9285_hw_pa_cal()
578 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); in ar9285_hw_pa_cal()
579 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); in ar9285_hw_pa_cal()
580 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); in ar9285_hw_pa_cal()
581 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); in ar9285_hw_pa_cal()
582 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); in ar9285_hw_pa_cal()
583 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); in ar9285_hw_pa_cal()
584 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); in ar9285_hw_pa_cal()
585 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); in ar9285_hw_pa_cal()
586 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); in ar9285_hw_pa_cal()
587 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9285_hw_pa_cal()
588 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9285_hw_pa_cal()
589 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); in ar9285_hw_pa_cal()
590 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); in ar9285_hw_pa_cal()
592 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9285_hw_pa_cal()
594 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); in ar9285_hw_pa_cal()
595 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); in ar9285_hw_pa_cal()
598 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
600 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
602 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
604 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
606 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
609 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); in ar9285_hw_pa_cal()
611 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
612 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); in ar9285_hw_pa_cal()
613 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); in ar9285_hw_pa_cal()
614 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); in ar9285_hw_pa_cal()
621 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) { in ar9285_hw_pa_cal()
622 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9285_hw_pa_cal()
623 ah->pacal_info.max_skipcount = in ar9285_hw_pa_cal()
624 2 * ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
625 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
627 ah->pacal_info.max_skipcount = 1; in ar9285_hw_pa_cal()
628 ah->pacal_info.skipcount = 0; in ar9285_hw_pa_cal()
629 ah->pacal_info.prev_offset = offset; in ar9285_hw_pa_cal()
632 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); in ar9285_hw_pa_cal()
633 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); in ar9285_hw_pa_cal()
635 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
637 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
638 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
640 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
643 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
645 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); in ar9285_hw_pa_cal()
648 static void ar9002_hw_pa_cal(struct ath_hw *ah, int is_reset) in ar9002_hw_pa_cal() argument
650 if (AR_SREV_9271(ah)) { in ar9002_hw_pa_cal()
651 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
652 ar9271_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
654 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
655 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_pa_cal()
656 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
657 ar9285_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
659 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
663 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah) in ar9002_hw_olc_temp_compensation() argument
666 ar9287_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
668 ar9280_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
671 static int ar9002_hw_calibrate(struct ath_hw *ah, in ar9002_hw_calibrate() argument
677 struct ath9k_cal_list *currCal = ah->cal_list_curr; in ar9002_hw_calibrate()
680 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF); in ar9002_hw_calibrate()
681 if (ah->caldata) in ar9002_hw_calibrate()
682 nfcal_pending = ah->caldata->nfcal_pending; in ar9002_hw_calibrate()
687 iscaldone = ar9002_hw_per_calibration(ah, chan, in ar9002_hw_calibrate()
690 ah->cal_list_curr = currCal = currCal->calNext; in ar9002_hw_calibrate()
694 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_calibrate()
705 if (ath9k_hw_getnf(ah, chan)) { in ar9002_hw_calibrate()
712 ath9k_hw_loadnf(ah, ah->curchan); in ar9002_hw_calibrate()
716 ath9k_hw_start_nfcal(ah, 0); in ar9002_hw_calibrate()
718 ar9002_hw_pa_cal(ah, 0); in ar9002_hw_calibrate()
719 ar9002_hw_olc_temp_compensation(ah); in ar9002_hw_calibrate()
727 static int ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_cl_cal() argument
729 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
731 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
732 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
733 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
735 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
736 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
737 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
743 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
744 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
745 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
747 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
748 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
749 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
750 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
751 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
758 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
759 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
760 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
765 static int ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_clc() argument
777 if (!(ar9285_hw_cl_cal(ah, chan))) in ar9285_hw_clc()
780 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), in ar9285_hw_clc()
784 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & in ar9285_hw_clc()
793 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
795 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
805 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5); in ar9285_hw_clc()
806 if (AR_SREV_9285E_20(ah)) { in ar9285_hw_clc()
807 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
811 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
815 retv = ar9285_hw_cl_cal(ah, chan); in ar9285_hw_clc()
816 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); in ar9285_hw_clc()
821 static int ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_init_cal() argument
823 if (AR_SREV_9271(ah)) { in ar9002_hw_init_cal()
824 if (!ar9285_hw_cl_cal(ah, chan)) in ar9002_hw_init_cal()
826 } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_cal()
827 if (!ar9285_hw_clc(ah, chan)) in ar9002_hw_init_cal()
830 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
831 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
832 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
834 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
839 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
840 REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar9002_hw_init_cal()
844 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
852 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
853 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
854 REG_SET_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
856 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
862 ar9002_hw_pa_cal(ah, 1); in ar9002_hw_init_cal()
865 ath9k_hw_start_nfcal(ah, 1); in ar9002_hw_init_cal()
867 if (ah->caldata) in ar9002_hw_init_cal()
868 ah->caldata->nfcal_pending = 1; in ar9002_hw_init_cal()
870 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9002_hw_init_cal()
873 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal()
874 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal()
876 if (AR_SREV_9160_10_OR_LATER(ah)) in ar9002_hw_init_cal()
877 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL; in ar9002_hw_init_cal()
879 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal()
880 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal()
882 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) { in ar9002_hw_init_cal()
883 INIT_CAL(&ah->adcgain_caldata); in ar9002_hw_init_cal()
884 INSERT_CAL(ah, &ah->adcgain_caldata); in ar9002_hw_init_cal()
889 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) { in ar9002_hw_init_cal()
890 INIT_CAL(&ah->adcdc_caldata); in ar9002_hw_init_cal()
891 INSERT_CAL(ah, &ah->adcdc_caldata); in ar9002_hw_init_cal()
896 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) { in ar9002_hw_init_cal()
897 INIT_CAL(&ah->iq_caldata); in ar9002_hw_init_cal()
898 INSERT_CAL(ah, &ah->iq_caldata); in ar9002_hw_init_cal()
903 ah->cal_list_curr = ah->cal_list; in ar9002_hw_init_cal()
905 if (ah->cal_list_curr) in ar9002_hw_init_cal()
906 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); in ar9002_hw_init_cal()
909 if (ah->caldata) in ar9002_hw_init_cal()
910 ah->caldata->CalValid = 0; in ar9002_hw_init_cal()
958 static void ar9002_hw_init_cal_settings(struct ath_hw *ah) in ar9002_hw_init_cal_settings() argument
960 if (AR_SREV_9100(ah)) { in ar9002_hw_init_cal_settings()
961 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
962 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
966 if (AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
967 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
968 ah->iq_caldata.calData = &iq_cal_single_sample; in ar9002_hw_init_cal_settings()
969 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
971 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
974 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
975 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
977 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
980 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
982 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal_settings()
983 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal_settings()
987 void ar9002_hw_attach_calib_ops(struct ath_hw *ah) in ar9002_hw_attach_calib_ops() argument
989 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_calib_ops()
990 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_calib_ops()