Lines Matching refs:PMC_MCR
29 #define PMC_MCR 0x30 macro
175 pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id)); in clk_sama7g5_master_set_parent()
176 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_parent()
187 pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id)); in clk_sama7g5_master_enable()
188 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_enable()
199 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_disable()
200 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_disable()
227 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_set_rate()
228 pmc_update_bits(master->base, PMC_MCR, in clk_sama7g5_master_set_rate()
246 pmc_write(master->base, PMC_MCR, master->id); in clk_sama7g5_master_get_rate()
247 pmc_read(master->base, PMC_MCR, &val); in clk_sama7g5_master_get_rate()
291 pmc_write(master->base, PMC_MCR, master->id); in at91_clk_sama7g5_register_master()
292 pmc_read(master->base, PMC_MCR, &val); in at91_clk_sama7g5_register_master()