Lines Matching +refs:def +refs:logical +refs:imm +refs:and +refs:reg
28 // and the other having a 20-bit displacement. Both instructions in
29 // the pair have the same DispKey and their DispSizes are "12" and "20"
36 // "reg" for <INSN>R and "mem" for <INSN>.
40 // MemKey identifies a targe reg-mem opcode, while MemType can be either
47 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
83 // True if the instruction is conditional and if the CC mask operand
90 // True if the instruction is the "logical" rather than "arithmetic" form,
91 // in cases where a distinction exists. Except for logical compares, if the
121 def getDisp12Opcode : InstrMapping {
130 def getDisp20Opcode : InstrMapping {
140 def getMemOpcode : InstrMapping {
144 let KeyCol = ["reg"];
149 def getTargetMemOpcode : InstrMapping {
158 def getTwoOperandOpcode : InstrMapping {
175 // bits<4> BDn : address operand n, which has a base and a displacement
176 // bits<m> XBDn : address operand n, which has an index, a base and a
178 // bits<m> VBDn : address operand n, which has a vector index, a base and a
185 // is often written between operands 1 and 2.
1772 // compare-and-branch instructions, or conditional move instructions),
1780 // is implied by the pattern name and not otherwise encoded at all.
1782 // We need the latter primarily for the assembler and disassembler, since the
1812 def CondAlways : CondVariant<15, "", 0>;
1815 def CondVariantO : CondVariant<1, "o", 0>;
1816 def CondVariantH : CondVariant<2, "h", 0>;
1817 def CondVariantP : CondVariant<2, "p", 1>;
1818 def CondVariantNLE : CondVariant<3, "nle", 0>;
1819 def CondVariantL : CondVariant<4, "l", 0>;
1820 def CondVariantM : CondVariant<4, "m", 1>;
1821 def CondVariantNHE : CondVariant<5, "nhe", 0>;
1822 def CondVariantLH : CondVariant<6, "lh", 0>;
1823 def CondVariantNE : CondVariant<7, "ne", 0>;
1824 def CondVariantNZ : CondVariant<7, "nz", 1>;
1825 def CondVariantE : CondVariant<8, "e", 0>;
1826 def CondVariantZ : CondVariant<8, "z", 1>;
1827 def CondVariantNLH : CondVariant<9, "nlh", 0>;
1828 def CondVariantHE : CondVariant<10, "he", 0>;
1829 def CondVariantNL : CondVariant<11, "nl", 0>;
1830 def CondVariantNM : CondVariant<11, "nm", 1>;
1831 def CondVariantLE : CondVariant<12, "le", 0>;
1832 def CondVariantNH : CondVariant<13, "nh", 0>;
1833 def CondVariantNP : CondVariant<13, "np", 1>;
1834 def CondVariantNO : CondVariant<14, "no", 0>;
1842 // Condition masks for integer instructions (e.g. compare-and-branch).
1844 // and that the low bit of the mask is therefore always 0. This means
1845 // that each condition has two names. Conditions "o" and "no" are not used.
1846 def IntCondVariantH : CondVariant<2, "h", 0>;
1847 def IntCondVariantNLE : CondVariant<2, "nle", 1>;
1848 def IntCondVariantL : CondVariant<4, "l", 0>;
1849 def IntCondVariantNHE : CondVariant<4, "nhe", 1>;
1850 def IntCondVariantLH : CondVariant<6, "lh", 0>;
1851 def IntCondVariantNE : CondVariant<6, "ne", 1>;
1852 def IntCondVariantE : CondVariant<8, "e", 0>;
1853 def IntCondVariantNLH : CondVariant<8, "nlh", 1>;
1854 def IntCondVariantHE : CondVariant<10, "he", 0>;
1855 def IntCondVariantNL : CondVariant<10, "nl", 1>;
1856 def IntCondVariantLE : CondVariant<12, "le", 0>;
1857 def IntCondVariantNH : CondVariant<12, "nh", 1>;
1870 // of the formats defined above and where <Category> describes the inputs
1871 // and outputs. "Cond" is used if the instruction is conditional,
1876 // One register output operand and no input operands.
1879 // Two register output operands and no input operands.
1891 // One output operand and one branch target. The instruction stores
1892 // the return address to the output operand and branches to the target.
1895 // Two input operands and one optional branch target. The instruction
1896 // compares the two input operands and branches or traps on the result.
1899 // One register output operand, one register input operand and one branch
1901 // in the destination register and branches on the result.
1904 // One register output operand, two register input operands and one branch
1906 // registers in the destination register and branches on the result.
1909 // One address input operand and two explicit output operands.
1911 // with the explicit operands giving the first and last register
1915 // Two explicit input register operands and an address operand.
1917 // with the explicit operands giving the first and last register
1921 // One value operand, one length operand and one address operand.
1927 // One register output operand and one address operand.
1933 // One register output operand and one input operand.
1936 // One address operand and one other input operand. The instruction
1943 // One register output operand and two input operands.
1946 // One address operand and two other input operands. The instruction
1953 // Two input operands and an implicit CC output operand.
1956 // One or two input operands and an implicit CC output operand. If
1961 // One register output operand and three input operands.
1967 // One register output operand and four input operands.
1970 // One output operand and two input operands, one of which is an address.
1971 // The instruction both reads from and writes to the address.
1974 // One output operand and three input operands, one of which is an address.
1975 // The instruction both reads from and writes to the address.
1978 // One output operand and five input operands. The first two operands
1979 // are registers and the other three are immediates.
1982 // One 4-bit immediate operand and one address operand. The immediate
1983 // operand is 1 for a load prefetch and 2 for a store prefetch.
1986 // One 4-bit immediate operand and two address operands.
1989 // and also determines the shape of any address operand.
1992 // one with <Category><Format> and one with <Category><Format>Y. The name
2153 RegisterOperand cls, ImmOpWithPattern imm>
2154 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2158 RegisterOperand cls, ImmOpWithPattern imm>
2159 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2163 RegisterOperand cls, ImmOpWithPattern imm>
2164 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2171 RegisterOperand cls, ImmOpWithPattern imm> {
2173 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2174 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2200 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2201 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2205 RegisterOperand cls, ImmOpWithPattern imm>
2207 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2211 RegisterOperand cls, ImmOpWithPattern imm>
2213 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2217 RegisterOperand cls, ImmOpWithPattern imm>
2218 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2225 RegisterOperand cls, ImmOpWithPattern imm> {
2227 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2228 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2244 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2245 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2279 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2280 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2284 RegisterOperand cls, ImmOpWithPattern imm>
2286 (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
2290 RegisterOperand cls, ImmOpWithPattern imm>
2292 (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
2296 RegisterOperand cls, ImmOpWithPattern imm>
2297 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2304 RegisterOperand cls, ImmOpWithPattern imm> {
2306 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2307 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2323 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2324 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2426 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2428 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2441 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2445 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2457 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2458 // However, BDXs have two extra operands and are therefore 6 units more
2492 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2494 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2517 def Align : InstVRX<opcode, (outs),
2521 def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
2572 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2574 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2580 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2584 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2594 // We therefore match the address in the same way as a normal store and
2597 ImmOpWithPattern imm>
2598 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2600 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2605 ImmOpWithPattern imm>
2606 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2608 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2613 ImmOpWithPattern imm>
2614 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2616 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2621 SDPatternOperator operator, ImmOpWithPattern imm> {
2624 def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2626 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2673 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2674 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2677 class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm>
2678 : InstI<opcode, (outs), (ins imm:$I1),
2725 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2727 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2743 let OpType = "reg";
2752 let OpType = "reg";
2773 RegisterOperand cls, ImmOpWithPattern imm>
2774 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2776 [(set cls:$R1, (operator imm:$I2))]>;
2779 RegisterOperand cls, ImmOpWithPattern imm>
2780 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2782 [(set cls:$R1, (operator imm:$I2))]>;
2790 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2791 // However, BDXs have two extra operands and are therefore 6 units more
2844 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2845 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2889 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2891 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2897 TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0>
2898 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2904 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm>
2905 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2934 // Declare a pair of instructions, one which sets CC and one which doesn't.
2935 // The CC-setting form ends with "S" and sets the low bit of M5.
2943 def "" : InstVRRa<opcode, (outs tr1.op:$V1),
2946 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
2948 def : InstAlias<mnemonic#"\t$V1, $V2",
2951 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
2957 def "" : InstVRRa<opcode, (outs VR128:$V1),
2960 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
2983 def Align : InstVRX<opcode, (outs VR128:$V1),
2987 def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
3006 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3007 // However, BDXs have two extra operands and are therefore 6 units more
3037 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
3038 : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3042 SDPatternOperator operator, ImmOpWithPattern imm>
3043 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3044 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
3102 let OpType = "reg";
3113 let OpType = "reg";
3124 let OpType = "reg";
3135 let OpType = "reg";
3143 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3146 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3155 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3158 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3177 RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm>
3178 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3186 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3187 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3241 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3242 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3278 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3279 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3283 RegisterOperand cls, ImmOpWithPattern imm>
3284 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3286 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3292 RegisterOperand cls, ImmOpWithPattern imm>
3293 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3295 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3299 ImmOpWithPattern imm> {
3302 def K : BinaryRIE<mnemonic##"k", opcode2, operator, cls, imm>,
3305 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3310 ImmOpWithPattern imm>
3312 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3314 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3324 ImmOpWithPattern imm>
3326 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3334 RegisterOperand cls, ImmOpWithPattern imm>
3335 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3344 RegisterOperand cls, ImmOpWithPattern imm> {
3346 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3347 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3351 RegisterOperand cls, ImmOpWithPattern imm>
3352 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3354 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3379 def K : BinaryRSY<mnemonic##"k", opcode2, operator, cls>,
3382 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3453 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3456 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3462 Operand imm, AddressingMode mode = bdaddr12only>
3463 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3465 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3471 Operand imm, AddressingMode mode = bdaddr20only>
3472 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3474 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3481 Operand imm> {
3484 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
3486 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
3569 // Declare a pair of instructions, one which sets CC and one which doesn't.
3570 // The CC-setting form ends with "S" and sets the low bit of M5.
3575 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3576 !and (modifier, 14)>;
3578 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3579 !add (!and (modifier, 14), 1)>;
3589 // Declare a pair of instructions, one which sets CC and one which doesn't.
3590 // The CC-setting form ends with "S" and sets the low bit of M5.
3598 def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3601 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3603 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3607 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
3612 def "" : InstVRRb<opcode, (outs VR128:$V1),
3615 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3648 // Declare a pair of instructions, one which sets CC and one which doesn't.
3649 // The CC-setting form ends with "S" and sets the low bit of M5.
3655 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3656 m5, !and (modifier, 14)>;
3658 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3659 m5, !add (!and (modifier, 14), 1)>;
3757 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3759 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
3810 let OpType = "reg";
3820 let OpType = "reg";
3825 RegisterOperand cls, ImmOpWithPattern imm>
3826 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3828 [(set CC, (operator cls:$R1, imm:$I2))]> {
3833 RegisterOperand cls, ImmOpWithPattern imm>
3834 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3836 [(set CC, (operator cls:$R1, imm:$I2))]> {
3847 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3848 // However, BDXs have two extra operands and are therefore 6 units more
3897 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3900 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3925 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3927 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3940 SDPatternOperator load, ImmOpWithPattern imm,
3942 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3944 [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
3950 SDPatternOperator load, ImmOpWithPattern imm>
3951 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3953 [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> {
3959 SDPatternOperator load, ImmOpWithPattern imm,
3961 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3963 [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
3970 ImmOpWithPattern imm> {
3973 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
3975 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
4028 SDPatternOperator operator, ImmOpWithPattern imm>
4029 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
4031 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
4089 ImmOpWithPattern imm>
4090 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4096 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4097 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
4102 ImmOpWithPattern imm>
4104 (ins cls1:$R1src, cls2:$R2src, imm:$M3),
4113 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4114 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
4151 let OpType = "reg";
4184 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4186 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4237 TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index>
4238 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4241 imm:$I2, index:$M3))]> {
4292 // Declare a pair of instructions, one which sets CC and one which doesn't.
4293 // The CC-setting form ends with "S" and sets the low bit of M5.
4300 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4301 imm32zx4even_timm, !and (modifier, 14)>;
4302 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4306 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
4307 imm32zx4even_timm, !add(!and (modifier, 14), 1)>;
4308 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4315 def "" : InstVRRb<opcode, (outs VR128:$V1),
4318 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4379 def "" : InstVRRd<opcode, (outs tr1.op:$V1),
4382 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4385 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4392 def "" : InstVRRd<opcode, (outs VR128:$V1),
4396 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4524 // Declare a pair of instructions, one which sets CC and one which doesn't.
4525 // The CC-setting form ends with "S" and sets the low bit of M6.
4532 def "" : QuaternaryVRRd<mnemonic, opcode, operator,
4534 imm32zx4even_timm, !and (modifier, 14)>;
4535 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4539 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc,
4541 imm32zx4even_timm, !add (!and (modifier, 14), 1)>;
4542 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4549 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
4550 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4565 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4566 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4567 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4580 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4581 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4635 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4637 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
4661 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
4662 // However, BDXs have two extra operands and are therefore 6 units more
4677 // A floating-point load-and test operation. Create both a normal unary
4678 // operation and one that acts as a comparison against zero.
4680 // have vector support, since load-and-test instructions will partially
4684 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4686 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
4707 ImmOpWithPattern imm>
4708 : Pseudo<(outs cls:$R1), (ins imm:$I2),
4709 [(set cls:$R1, (operator imm:$I2))]>;
4731 let OpType = "reg";
4736 ImmOpWithPattern imm>
4737 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
4738 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4744 ImmOpWithPattern imm>
4745 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
4746 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
4750 RegisterOperand cls, ImmOpWithPattern imm> {
4753 def K : BinaryRIEPseudo<operator, cls, imm>,
4756 def "" : BinaryRIPseudo<operator, cls, imm>,
4763 // be converted directly to a target 2-address reg/mem instruction.
4780 ImmOpWithPattern imm>
4781 : Pseudo<(outs), (ins cls:$R1, imm:$I2),
4782 [(set CC, (operator cls:$R1, imm:$I2))]> {
4799 class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm>
4800 : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
4801 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
4833 class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
4835 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
4836 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
4908 def "" : Pseudo<(outs),
4913 def Inv : Pseudo<(outs),
4921 // OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
4938 class AtomicLoadBinaryImm32<SDPatternOperator operator, ImmOpWithPattern imm>
4939 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
4942 class AtomicLoadBinaryImm64<SDPatternOperator operator, ImmOpWithPattern imm>
4943 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
4945 // OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND
4965 class AtomicLoadWBinaryImm<SDPatternOperator operator, ImmOpWithPattern imm>
4966 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
5000 ImmOpWithPattern imm>
5001 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5002 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5008 ImmOpWithPattern imm>
5009 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5010 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5020 ImmOpWithPattern imm>
5021 : Alias<4, (outs), (ins cls:$R1, imm:$I2),
5022 [(set CC, (operator cls:$R1, imm:$I2))]> {
5035 // Multiclasses that emit both real and pseudo instructions
5043 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5048 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>;
5056 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
5063 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
5066 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>;
5070 // and associated pseudo instructions for operating on blocks of any size.
5071 // The Sequence form uses a straight-line sequence of instructions and
5076 def "" : SideEffectBinarySSa<mnemonic, opcode>;
5078 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5082 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5092 def "" : SideEffectBinarySSa<mnemonic, opcode>;
5094 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5098 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5107 // number of bytes at a time and sets CC to 3 if the instruction needs
5113 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
5115 def Loop : Pseudo<(outs GR64:$end),