Lines Matching refs:COMP
33 #define COMP TGSI_OUTPUT_COMPONENTWISE macro
40 { 1, 1, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL },
41 { 1, 1, 0, 0, 0, 0, COMP, "MOV", TGSI_OPCODE_MOV },
47 { 1, 2, 0, 0, 0, 0, COMP, "MUL", TGSI_OPCODE_MUL },
48 { 1, 2, 0, 0, 0, 0, COMP, "ADD", TGSI_OPCODE_ADD },
52 { 1, 2, 0, 0, 0, 0, COMP, "MIN", TGSI_OPCODE_MIN },
53 { 1, 2, 0, 0, 0, 0, COMP, "MAX", TGSI_OPCODE_MAX },
54 { 1, 2, 0, 0, 0, 0, COMP, "SLT", TGSI_OPCODE_SLT },
55 { 1, 2, 0, 0, 0, 0, COMP, "SGE", TGSI_OPCODE_SGE },
56 { 1, 3, 0, 0, 0, 0, COMP, "MAD", TGSI_OPCODE_MAD },
57 { 1, 2, 0, 0, 0, 0, COMP, "SUB", TGSI_OPCODE_SUB },
58 { 1, 3, 0, 0, 0, 0, COMP, "LRP", TGSI_OPCODE_LRP },
59 { 1, 3, 0, 0, 0, 0, COMP, "FMA", TGSI_OPCODE_FMA },
64 { 1, 1, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
65 { 1, 3, 0, 0, 0, 0, COMP, "", 25 }, /* removed */
66 { 1, 1, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
67 { 1, 1, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
71 { 1, 2, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
73 { 1, 1, 0, 0, 0, 0, COMP, "ABS", TGSI_OPCODE_ABS },
77 { 1, 1, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
78 { 1, 1, 0, 0, 0, 0, COMP, "DDY", TGSI_OPCODE_DDY },
80 { 1, 1, 0, 0, 0, 0, COMP, "PK2H", TGSI_OPCODE_PK2H },
81 { 1, 1, 0, 0, 0, 0, COMP, "PK2US", TGSI_OPCODE_PK2US },
82 { 1, 1, 0, 0, 0, 0, COMP, "PK4B", TGSI_OPCODE_PK4B },
83 { 1, 1, 0, 0, 0, 0, COMP, "PK4UB", TGSI_OPCODE_PK4UB },
85 { 1, 2, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
87 { 1, 2, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },
89 { 1, 2, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE },
90 { 1, 2, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE },
95 { 1, 1, 0, 0, 0, 0, COMP, "UP2H", TGSI_OPCODE_UP2H },
96 { 1, 1, 0, 0, 0, 0, COMP, "UP2US", TGSI_OPCODE_UP2US },
97 { 1, 1, 0, 0, 0, 0, COMP, "UP4B", TGSI_OPCODE_UP4B },
98 { 1, 1, 0, 0, 0, 0, COMP, "UP4UB", TGSI_OPCODE_UP4UB },
101 { 1, 1, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
105 { 1, 1, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG },
106 { 1, 3, 0, 0, 0, 0, COMP, "CMP", TGSI_OPCODE_CMP },
110 { 1, 2, 0, 0, 0, 0, COMP, "DIV", TGSI_OPCODE_DIV },
119 { 1, 1, 0, 0, 0, 0, COMP, "DDX_FINE", TGSI_OPCODE_DDX_FINE },
120 { 1, 1, 0, 0, 0, 0, COMP, "DDY_FINE", TGSI_OPCODE_DDY_FINE },
123 { 1, 1, 0, 0, 0, 0, COMP, "CEIL", TGSI_OPCODE_CEIL },
124 { 1, 1, 0, 0, 0, 0, COMP, "I2F", TGSI_OPCODE_I2F },
125 { 1, 1, 0, 0, 0, 0, COMP, "NOT", TGSI_OPCODE_NOT },
126 { 1, 1, 0, 0, 0, 0, COMP, "TRUNC", TGSI_OPCODE_TRUNC },
127 { 1, 2, 0, 0, 0, 0, COMP, "SHL", TGSI_OPCODE_SHL },
129 { 1, 2, 0, 0, 0, 0, COMP, "AND", TGSI_OPCODE_AND },
130 { 1, 2, 0, 0, 0, 0, COMP, "OR", TGSI_OPCODE_OR },
131 { 1, 2, 0, 0, 0, 0, COMP, "MOD", TGSI_OPCODE_MOD },
132 { 1, 2, 0, 0, 0, 0, COMP, "XOR", TGSI_OPCODE_XOR },
133 { 0, 0, 0, 0, 0, 0, COMP, "", 93 }, /* removed */
148 { 1, 2, 0, 0, 0, 0, COMP, "FSEQ", TGSI_OPCODE_FSEQ },
149 { 1, 2, 0, 0, 0, 0, COMP, "FSGE", TGSI_OPCODE_FSGE },
150 { 1, 2, 0, 0, 0, 0, COMP, "FSLT", TGSI_OPCODE_FSLT },
151 { 1, 2, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE },
158 { 1, 3, 0, 0, 0, 0, COMP, "DFMA", TGSI_OPCODE_DFMA },
159 { 1, 1, 0, 0, 0, 0, COMP, "F2I", TGSI_OPCODE_F2I },
160 { 1, 2, 0, 0, 0, 0, COMP, "IDIV", TGSI_OPCODE_IDIV },
161 { 1, 2, 0, 0, 0, 0, COMP, "IMAX", TGSI_OPCODE_IMAX },
162 { 1, 2, 0, 0, 0, 0, COMP, "IMIN", TGSI_OPCODE_IMIN },
163 { 1, 1, 0, 0, 0, 0, COMP, "INEG", TGSI_OPCODE_INEG },
164 { 1, 2, 0, 0, 0, 0, COMP, "ISGE", TGSI_OPCODE_ISGE },
165 { 1, 2, 0, 0, 0, 0, COMP, "ISHR", TGSI_OPCODE_ISHR },
166 { 1, 2, 0, 0, 0, 0, COMP, "ISLT", TGSI_OPCODE_ISLT },
167 { 1, 1, 0, 0, 0, 0, COMP, "F2U", TGSI_OPCODE_F2U },
168 { 1, 1, 0, 0, 0, 0, COMP, "U2F", TGSI_OPCODE_U2F },
169 { 1, 2, 0, 0, 0, 0, COMP, "UADD", TGSI_OPCODE_UADD },
170 { 1, 2, 0, 0, 0, 0, COMP, "UDIV", TGSI_OPCODE_UDIV },
171 { 1, 3, 0, 0, 0, 0, COMP, "UMAD", TGSI_OPCODE_UMAD },
172 { 1, 2, 0, 0, 0, 0, COMP, "UMAX", TGSI_OPCODE_UMAX },
173 { 1, 2, 0, 0, 0, 0, COMP, "UMIN", TGSI_OPCODE_UMIN },
174 { 1, 2, 0, 0, 0, 0, COMP, "UMOD", TGSI_OPCODE_UMOD },
175 { 1, 2, 0, 0, 0, 0, COMP, "UMUL", TGSI_OPCODE_UMUL },
176 { 1, 2, 0, 0, 0, 0, COMP, "USEQ", TGSI_OPCODE_USEQ },
177 { 1, 2, 0, 0, 0, 0, COMP, "USGE", TGSI_OPCODE_USGE },
178 { 1, 2, 0, 0, 0, 0, COMP, "USHR", TGSI_OPCODE_USHR },
179 { 1, 2, 0, 0, 0, 0, COMP, "USLT", TGSI_OPCODE_USLT },
180 { 1, 2, 0, 0, 0, 0, COMP, "USNE", TGSI_OPCODE_USNE },
198 { 1, 1, 0, 0, 0, 0, COMP, "UARL", TGSI_OPCODE_UARL },
199 { 1, 3, 0, 0, 0, 0, COMP, "UCMP", TGSI_OPCODE_UCMP },
200 { 1, 1, 0, 0, 0, 0, COMP, "IABS", TGSI_OPCODE_IABS },
201 { 1, 1, 0, 0, 0, 0, COMP, "ISSG", TGSI_OPCODE_ISSG },
222 { 1, 2, 0, 0, 0, 0, COMP, "IMUL_HI", TGSI_OPCODE_IMUL_HI },
223 { 1, 2, 0, 0, 0, 0, COMP, "UMUL_HI", TGSI_OPCODE_UMUL_HI },
226 { 1, 3, 0, 0, 0, 0, COMP, "IBFE", TGSI_OPCODE_IBFE },
227 { 1, 3, 0, 0, 0, 0, COMP, "UBFE", TGSI_OPCODE_UBFE },
228 { 1, 4, 0, 0, 0, 0, COMP, "BFI", TGSI_OPCODE_BFI },
229 { 1, 1, 0, 0, 0, 0, COMP, "BREV", TGSI_OPCODE_BREV },
230 { 1, 1, 0, 0, 0, 0, COMP, "POPC", TGSI_OPCODE_POPC },
231 { 1, 1, 0, 0, 0, 0, COMP, "LSB", TGSI_OPCODE_LSB },
232 { 1, 1, 0, 0, 0, 0, COMP, "IMSB", TGSI_OPCODE_IMSB },
233 { 1, 1, 0, 0, 0, 0, COMP, "UMSB", TGSI_OPCODE_UMSB },
237 { 1, 1, 0, 0, 0, 0, COMP, "F2D", TGSI_OPCODE_F2D },
238 { 1, 1, 0, 0, 0, 0, COMP, "D2F", TGSI_OPCODE_D2F },
239 { 1, 1, 0, 0, 0, 0, COMP, "DABS", TGSI_OPCODE_DABS },
240 { 1, 1, 0, 0, 0, 0, COMP, "DNEG", TGSI_OPCODE_DNEG },
241 { 1, 2, 0, 0, 0, 0, COMP, "DADD", TGSI_OPCODE_DADD },
242 { 1, 2, 0, 0, 0, 0, COMP, "DMUL", TGSI_OPCODE_DMUL },
243 { 1, 2, 0, 0, 0, 0, COMP, "DMAX", TGSI_OPCODE_DMAX },
244 { 1, 2, 0, 0, 0, 0, COMP, "DMIN", TGSI_OPCODE_DMIN },
245 { 1, 2, 0, 0, 0, 0, COMP, "DSLT", TGSI_OPCODE_DSLT },
246 { 1, 2, 0, 0, 0, 0, COMP, "DSGE", TGSI_OPCODE_DSGE },
247 { 1, 2, 0, 0, 0, 0, COMP, "DSEQ", TGSI_OPCODE_DSEQ },
248 { 1, 2, 0, 0, 0, 0, COMP, "DSNE", TGSI_OPCODE_DSNE },
249 { 1, 1, 0, 0, 0, 0, COMP, "DRCP", TGSI_OPCODE_DRCP },
250 { 1, 1, 0, 0 ,0, 0, COMP, "DSQRT", TGSI_OPCODE_DSQRT },
251 { 1, 3, 0, 0 ,0, 0, COMP, "DMAD", TGSI_OPCODE_DMAD },
252 { 1, 1, 0, 0, 0, 0, COMP, "DFRAC", TGSI_OPCODE_DFRAC},
253 { 1, 2, 0, 0, 0, 0, COMP, "DLDEXP", TGSI_OPCODE_DLDEXP},
254 { 2, 1, 0, 0, 0, 0, COMP, "DFRACEXP", TGSI_OPCODE_DFRACEXP},
255 { 1, 1, 0, 0, 0, 0, COMP, "D2I", TGSI_OPCODE_D2I },
256 { 1, 1, 0, 0, 0, 0, COMP, "I2D", TGSI_OPCODE_I2D },
257 { 1, 1, 0, 0, 0, 0, COMP, "D2U", TGSI_OPCODE_D2U },
258 { 1, 1, 0, 0, 0, 0, COMP, "U2D", TGSI_OPCODE_U2D },
259 { 1, 1, 0, 0 ,0, 0, COMP, "DRSQ", TGSI_OPCODE_DRSQ },
260 { 1, 1, 0, 0, 0, 0, COMP, "DTRUNC", TGSI_OPCODE_DTRUNC },
261 { 1, 1, 0, 0, 0, 0, COMP, "DCEIL", TGSI_OPCODE_DCEIL },
262 { 1, 1, 0, 0, 0, 0, COMP, "DFLR", TGSI_OPCODE_DFLR },
263 { 1, 1, 0, 0, 0, 0, COMP, "DROUND", TGSI_OPCODE_DROUND },
264 { 1, 1, 0, 0, 0, 0, COMP, "DSSG", TGSI_OPCODE_DSSG },
265 { 1, 2, 0, 0, 0, 0, COMP, "DDIV", TGSI_OPCODE_DDIV },
268 { 1, 1, 0, 0, 0, 0, COMP, "I64ABS", TGSI_OPCODE_I64ABS },
269 { 1, 1, 0, 0, 0, 0, COMP, "I64NEG", TGSI_OPCODE_I64NEG },
270 { 1, 1, 0, 0, 0, 0, COMP, "I64SSG", TGSI_OPCODE_I64SSG },
271 { 1, 2, 0, 0, 0, 0, COMP, "I64SLT", TGSI_OPCODE_I64SLT },
272 { 1, 2, 0, 0, 0, 0, COMP, "I64SGE", TGSI_OPCODE_I64SGE },
273 { 1, 2, 0, 0, 0, 0, COMP, "I64MIN", TGSI_OPCODE_I64MIN },
274 { 1, 2, 0, 0, 0, 0, COMP, "I64MAX", TGSI_OPCODE_I64MAX },
275 { 1, 2, 0, 0, 0, 0, COMP, "I64SHR", TGSI_OPCODE_I64SHR },
276 { 1, 2, 0, 0, 0, 0, COMP, "I64DIV", TGSI_OPCODE_I64DIV },
277 { 1, 2, 0, 0, 0, 0, COMP, "I64MOD", TGSI_OPCODE_I64MOD },
278 { 1, 1, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 },
279 { 1, 1, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 },
280 { 1, 1, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 },
281 { 1, 1, 0, 0, 0, 0, COMP, "D2I64", TGSI_OPCODE_D2I64 },
282 { 1, 1, 0, 0, 0, 0, COMP, "I642F", TGSI_OPCODE_I642F },
283 { 1, 1, 0, 0, 0, 0, COMP, "I642D", TGSI_OPCODE_I642D },
285 { 1, 2, 0, 0, 0, 0, COMP, "U64ADD", TGSI_OPCODE_U64ADD },
286 { 1, 2, 0, 0, 0, 0, COMP, "U64MUL", TGSI_OPCODE_U64MUL },
287 { 1, 2, 0, 0, 0, 0, COMP, "U64SEQ", TGSI_OPCODE_U64SEQ },
288 { 1, 2, 0, 0, 0, 0, COMP, "U64SNE", TGSI_OPCODE_U64SNE },
289 { 1, 2, 0, 0, 0, 0, COMP, "U64SLT", TGSI_OPCODE_U64SLT },
290 { 1, 2, 0, 0, 0, 0, COMP, "U64SGE", TGSI_OPCODE_U64SGE },
291 { 1, 2, 0, 0, 0, 0, COMP, "U64MIN", TGSI_OPCODE_U64MIN },
292 { 1, 2, 0, 0, 0, 0, COMP, "U64MAX", TGSI_OPCODE_U64MAX },
293 { 1, 2, 0, 0, 0, 0, COMP, "U64SHL", TGSI_OPCODE_U64SHL },
294 { 1, 2, 0, 0, 0, 0, COMP, "U64SHR", TGSI_OPCODE_U64SHR },
295 { 1, 2, 0, 0, 0, 0, COMP, "U64DIV", TGSI_OPCODE_U64DIV },
296 { 1, 2, 0, 0, 0, 0, COMP, "U64MOD", TGSI_OPCODE_U64MOD },
297 { 1, 1, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 },
298 { 1, 1, 0, 0, 0, 0, COMP, "D2U64", TGSI_OPCODE_D2U64 },
299 { 1, 1, 0, 0, 0, 0, COMP, "U642F", TGSI_OPCODE_U642F },
300 { 1, 1, 0, 0, 0, 0, COMP, "U642D", TGSI_OPCODE_U642D }