98 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\  argument
99 	.enable_reg = SRI(reg1, block, reg_num),\
101 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
103 		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
104 		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
106 	.ack_reg = SRI(reg2, block, reg_num),\
108 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
110 		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
112 #define hpd_int_entry(reg_num)\  argument
113 	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
114 		IRQ_REG_ENTRY(HPD, reg_num,\
117 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
121 #define hpd_rx_int_entry(reg_num)\  argument
122 	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
123 		IRQ_REG_ENTRY(HPD, reg_num,\
126 		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
129 #define pflip_int_entry(reg_num)\  argument
130 	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
131 		IRQ_REG_ENTRY(DCP, reg_num, \
134 		.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
138 #define vupdate_int_entry(reg_num)\  argument
139 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
140 		IRQ_REG_ENTRY(CRTC, reg_num,\
146 #define vblank_int_entry(reg_num)\  argument
147 	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
148 		IRQ_REG_ENTRY(CRTC, reg_num,\
152 		.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
160 #define i2c_int_entry(reg_num) \  argument
161 	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
163 #define dp_sink_int_entry(reg_num) \  argument
164 	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
166 #define gpio_pad_int_entry(reg_num) \  argument
167 	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
169 #define dc_underflow_int_entry(reg_num) \  argument
170 	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()