Lines Matching refs:BIT_5
184 #define BIT_5 (1 << 5) macro
302 #define PCI_EXT_PATCH_1 BIT_5
366 #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
796 #define CS_STOP_DONE BIT_5 /* Stop Master is finished */
809 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
839 #define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */
872 #define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
933 #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */
987 #define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */
1072 #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */
1080 #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */
1108 #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
1166 #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */
1173 #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */
1230 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5
1351 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-T Half Duplex */
1358 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1429 #define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */
1454 #define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */
1548 #define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */
1809 #define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */
1824 #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */
1886 #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/
1894 #define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */
1907 #define GMR_FS_MII_ERR BIT_5 /* MII Error */
1964 #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
1983 #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
1999 #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
2026 #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
2062 #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
2096 #define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */