Lines Matching refs:Reg
61 void MachineOperand::setReg(Register Reg) { in setReg() argument
62 if (getReg() == Reg) in setReg()
74 SmallContents.RegNo = Reg; in setReg()
80 SmallContents.RegNo = Reg; in setReg()
83 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx, in substVirtReg() argument
85 assert(Reg.isVirtual()); in substVirtReg()
88 setReg(Reg); in substVirtReg()
93 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) { in substPhysReg() argument
94 assert(Register::isPhysicalRegister(Reg)); in substPhysReg()
96 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
103 setReg(Reg); in substPhysReg()
273 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, in ChangeToRegister() argument
294 SmallContents.RegNo = Reg; in ChangeToRegister()
305 Contents.Reg.Prev = nullptr; in ChangeToRegister()
498 if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true)) in printCFIRegister() local
499 OS << printReg(*Reg, TRI); in printCFIRegister()
805 Register Reg = getReg(); in print() local
827 if (Reg.isVirtual()) { in print()
833 OS << printReg(Reg, TRI, 0, MRI); in print()
842 if (Reg.isVirtual()) { in print()
845 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) { in print()
847 OS << printRegClassOrBank(Reg, MRI, TRI); in print()
964 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { in print() local
965 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { in print()
968 OS << printReg(Reg, TRI); in print()