431     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anon3fa02a340111::X86AsmParser::IntelExprStateMachine
465     unsigned getBaseReg() const { return BaseReg; }  in getBaseReg()
681           if (!BaseReg) {  in onPlus()
682             BaseReg = TmpReg;  in onPlus()
740           if (!BaseReg) {  in onMinus()
741             BaseReg = TmpReg;  in onMinus()
985           if (!BaseReg) {  in onRBrac()
986             BaseReg = TmpReg;  in onRBrac()
1146                                unsigned BaseReg, unsigned IndexReg,
1295 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1302   if (BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1303       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||  in CheckBaseRegAndIndexRegAndScale()
1304         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1305         X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1306         X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {  in CheckBaseRegAndIndexRegAndScale()
1323   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1332   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1333       (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&  in CheckBaseRegAndIndexRegAndScale()
1334                        BaseReg != X86::SI && BaseReg != X86::DI))) {  in CheckBaseRegAndIndexRegAndScale()
1339   if (BaseReg == 0 &&  in CheckBaseRegAndIndexRegAndScale()
1345   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1346     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1353     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1360     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexRegAndScale()
1366       if ((BaseReg != X86::BX && BaseReg != X86::BP) ||  in CheckBaseRegAndIndexRegAndScale()
1375   if (!Is64BitMode && BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1376       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {  in CheckBaseRegAndIndexRegAndScale()
1685         unsigned OrigReg = OrigOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1686         unsigned FinalReg = FinalOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1720         FinalOp.Mem.BaseReg = FinalReg;  in VerifyAndAdjustOperands()
1749                                            unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1780     if (BaseReg || IndexReg) {  in CreateMemForMSInlineAsm()
1783                                                BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1787       BaseReg = 1; // Make isAbsMem() false  in CreateMemForMSInlineAsm()
1790       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2588   unsigned BaseReg = SM.getBaseReg();  in parseIntelOperand()  local
2590   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2591     BaseReg = 0;  in parseIntelOperand()
2596   if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&  in parseIntelOperand()
2598     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2606       (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2607        X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2608        X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))  in parseIntelOperand()
2609     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2622   if ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in parseIntelOperand()
2624     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2626   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2627       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2633     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,  in parseIntelOperand()
2652       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2674   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2676         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
2977   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2989     BaseReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2990     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)  in ParseMemOperand()
3018         if (BaseReg == X86::RIP)  in ParseMemOperand()
3036             if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
3054   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3061   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3070   if (BaseReg || IndexReg) {  in ParseMemOperand()
3073       bool Is64 = X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||  in ParseMemOperand()
3075       bool Is16 = X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg);  in ParseMemOperand()
3094   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3096                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()