Lines Matching refs:SP
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_f64()
96 Reg = SP::I0 + Offset/8; in CC_Sparc64_Full()
99 Reg = SP::D0 + Offset/8; in CC_Sparc64_Full()
102 Reg = SP::F1 + Offset/4; in CC_Sparc64_Full()
105 Reg = SP::Q0 + Offset/16; in CC_Sparc64_Full()
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, in CC_Sparc64_Half()
141 unsigned Reg = SP::I0 + Offset/8; in CC_Sparc64_Half()
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); in toCallerWindow()
165 if (Reg >= SP::I0 && Reg <= SP::I7) in toCallerWindow()
166 return Reg - SP::I0 + SP::O0; in toCallerWindow()
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); in LowerReturn_32()
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); in LowerReturn_32()
378 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
395 &SP::IntRegsRegClass); in LowerFormalArguments_32()
404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
488 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in LowerFormalArguments_32()
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments_32()
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64()
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
1030 unsigned IReg = SP::I0 + Offset/8; in fixupVariableFloatArgs()
1129 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1131 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); in LowerCall_64()
1181 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); in LowerCall_64()
1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1579 setExceptionPointerRegister(SP::I0); in SparcTargetLowering()
1580 setExceptionSelectorRegister(SP::I1); in SparcTargetLowering()
1582 setStackPointerRegisterToSaveRestore(SP::O6); in SparcTargetLowering()
1899 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); in LowerGlobalTLSAddress()
1909 Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); in LowerGlobalTLSAddress()
1922 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); in LowerGlobalTLSAddress()
1955 DAG.getRegister(SP::G7, PtrVT), Offset, in LowerGlobalTLSAddress()
1968 DAG.getRegister(SP::G7, PtrVT), Offset); in LowerGlobalTLSAddress()
2374 DAG.getRegister(SP::I6, TLI.getPointerTy()), in LowerVASTART()
2411 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC()
2412 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); in LowerDYNAMIC_STACKALLOC() local
2413 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2414 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
2442 unsigned FrameReg = SP::I6; in getFRAMEADDR()
2499 unsigned RetReg = MF.addLiveIn(SP::I7, in LowerRETURNADDR()
2531 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2533 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2540 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2542 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2576 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); in LowerF128Load()
2577 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); in LowerF128Load()
2604 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); in LowerF128Store()
2605 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); in LowerF128Store()
2656 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2658 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
2667 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
2669 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
2847 case SP::SELECT_CC_Int_ICC: in EmitInstrWithCustomInserter()
2848 case SP::SELECT_CC_FP_ICC: in EmitInstrWithCustomInserter()
2849 case SP::SELECT_CC_DFP_ICC: in EmitInstrWithCustomInserter()
2850 case SP::SELECT_CC_QFP_ICC: in EmitInstrWithCustomInserter()
2851 return expandSelectCC(MI, BB, SP::BCOND); in EmitInstrWithCustomInserter()
2852 case SP::SELECT_CC_Int_FCC: in EmitInstrWithCustomInserter()
2853 case SP::SELECT_CC_FP_FCC: in EmitInstrWithCustomInserter()
2854 case SP::SELECT_CC_DFP_FCC: in EmitInstrWithCustomInserter()
2855 case SP::SELECT_CC_QFP_FCC: in EmitInstrWithCustomInserter()
2856 return expandSelectCC(MI, BB, SP::FBCOND); in EmitInstrWithCustomInserter()
2858 case SP::ATOMIC_LOAD_ADD_32: in EmitInstrWithCustomInserter()
2859 return expandAtomicRMW(MI, BB, SP::ADDrr); in EmitInstrWithCustomInserter()
2860 case SP::ATOMIC_LOAD_ADD_64: in EmitInstrWithCustomInserter()
2861 return expandAtomicRMW(MI, BB, SP::ADDXrr); in EmitInstrWithCustomInserter()
2862 case SP::ATOMIC_LOAD_SUB_32: in EmitInstrWithCustomInserter()
2863 return expandAtomicRMW(MI, BB, SP::SUBrr); in EmitInstrWithCustomInserter()
2864 case SP::ATOMIC_LOAD_SUB_64: in EmitInstrWithCustomInserter()
2865 return expandAtomicRMW(MI, BB, SP::SUBXrr); in EmitInstrWithCustomInserter()
2866 case SP::ATOMIC_LOAD_AND_32: in EmitInstrWithCustomInserter()
2867 return expandAtomicRMW(MI, BB, SP::ANDrr); in EmitInstrWithCustomInserter()
2868 case SP::ATOMIC_LOAD_AND_64: in EmitInstrWithCustomInserter()
2869 return expandAtomicRMW(MI, BB, SP::ANDXrr); in EmitInstrWithCustomInserter()
2870 case SP::ATOMIC_LOAD_OR_32: in EmitInstrWithCustomInserter()
2871 return expandAtomicRMW(MI, BB, SP::ORrr); in EmitInstrWithCustomInserter()
2872 case SP::ATOMIC_LOAD_OR_64: in EmitInstrWithCustomInserter()
2873 return expandAtomicRMW(MI, BB, SP::ORXrr); in EmitInstrWithCustomInserter()
2874 case SP::ATOMIC_LOAD_XOR_32: in EmitInstrWithCustomInserter()
2875 return expandAtomicRMW(MI, BB, SP::XORrr); in EmitInstrWithCustomInserter()
2876 case SP::ATOMIC_LOAD_XOR_64: in EmitInstrWithCustomInserter()
2877 return expandAtomicRMW(MI, BB, SP::XORXrr); in EmitInstrWithCustomInserter()
2878 case SP::ATOMIC_LOAD_NAND_32: in EmitInstrWithCustomInserter()
2879 return expandAtomicRMW(MI, BB, SP::ANDrr); in EmitInstrWithCustomInserter()
2880 case SP::ATOMIC_LOAD_NAND_64: in EmitInstrWithCustomInserter()
2881 return expandAtomicRMW(MI, BB, SP::ANDXrr); in EmitInstrWithCustomInserter()
2883 case SP::ATOMIC_SWAP_64: in EmitInstrWithCustomInserter()
2886 case SP::ATOMIC_LOAD_MAX_32: in EmitInstrWithCustomInserter()
2887 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G); in EmitInstrWithCustomInserter()
2888 case SP::ATOMIC_LOAD_MAX_64: in EmitInstrWithCustomInserter()
2889 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G); in EmitInstrWithCustomInserter()
2890 case SP::ATOMIC_LOAD_MIN_32: in EmitInstrWithCustomInserter()
2891 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE); in EmitInstrWithCustomInserter()
2892 case SP::ATOMIC_LOAD_MIN_64: in EmitInstrWithCustomInserter()
2893 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE); in EmitInstrWithCustomInserter()
2894 case SP::ATOMIC_LOAD_UMAX_32: in EmitInstrWithCustomInserter()
2895 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU); in EmitInstrWithCustomInserter()
2896 case SP::ATOMIC_LOAD_UMAX_64: in EmitInstrWithCustomInserter()
2897 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU); in EmitInstrWithCustomInserter()
2898 case SP::ATOMIC_LOAD_UMIN_32: in EmitInstrWithCustomInserter()
2899 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU); in EmitInstrWithCustomInserter()
2900 case SP::ATOMIC_LOAD_UMIN_64: in EmitInstrWithCustomInserter()
2901 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU); in EmitInstrWithCustomInserter()
2958 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) in expandSelectCC()
2997 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); in expandAtomicRMW()
2999 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in expandAtomicRMW()
3002 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) in expandAtomicRMW()
3029 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg) in expandAtomicRMW()
3036 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg); in expandAtomicRMW()
3044 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 || in expandAtomicRMW()
3045 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) { in expandAtomicRMW()
3048 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); in expandAtomicRMW()
3051 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) in expandAtomicRMW()
3054 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); in expandAtomicRMW()
3055 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) in expandAtomicRMW()
3146 return std::make_pair(0U, &SP::IntRegsRegClass); in getRegForInlineAsmConstraint()