Lines Matching refs:OS
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
65 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
71 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
81 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
83 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
84 OS << "#undef GET_REGINFO_ENUM\n"; in runEnums()
86 OS << "namespace llvm {\n\n"; in runEnums()
88 OS << "class MCRegisterClass;\n" in runEnums()
93 OS << "namespace " << Namespace << " {\n"; in runEnums()
94 OS << "enum {\n NoRegister,\n"; in runEnums()
97 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
100 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
101 OS << "};\n"; in runEnums()
103 OS << "}\n"; in runEnums()
112 OS << "\n// Register classes\n"; in runEnums()
114 OS << "namespace " << Namespace << " {\n"; in runEnums()
115 OS << "enum {\n"; in runEnums()
117 OS << " " << RC.getName() << "RegClassID" in runEnums()
119 OS << "\n };\n"; in runEnums()
121 OS << "}\n"; in runEnums()
128 OS << "\n// Register alternate name indices\n"; in runEnums()
130 OS << "namespace " << Namespace << " {\n"; in runEnums()
131 OS << "enum {\n"; in runEnums()
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
135 OS << "};\n"; in runEnums()
137 OS << "}\n"; in runEnums()
142 OS << "\n// Subregister indices\n"; in runEnums()
145 OS << "namespace " << Namespace << " {\n"; in runEnums()
146 OS << "enum {\n NoSubRegister,\n"; in runEnums()
149 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
150 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
152 OS << "}\n"; in runEnums()
155 OS << "} // End llvm namespace\n"; in runEnums()
156 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
159 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
160 OS << Val; in printInt()
173 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
178 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
185 OS << " {0, 0"; in EmitRegUnitPressure()
189 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
192 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
194 OS << " };\n" in EmitRegUnitPressure()
206 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
212 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
217 OS << RU.Weight << ", "; in EmitRegUnitPressure()
219 OS << "};\n" in EmitRegUnitPressure()
223 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
226 OS << "}\n\n"; in EmitRegUnitPressure()
228 OS << "\n" in EmitRegUnitPressure()
233 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
241 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
243 OS << " nullptr };\n" in EmitRegUnitPressure()
247 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
255 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
258 OS << " };\n" in EmitRegUnitPressure()
282 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
284 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
285 OS << "};\n\n"; in EmitRegUnitPressure()
287 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
292 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
295 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
297 OS << "};\n" in EmitRegUnitPressure()
301 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
308 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
312 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
315 OS << "};\n" in EmitRegUnitPressure()
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
349 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
354 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
355 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
356 OS << i << "Dwarf2L[]"; in EmitRegMappingTables()
359 OS << " = {\n"; in EmitRegMappingTables()
374 OS << " { " << I->first << "U, " << getQualifiedName(I->second) in EmitRegMappingTables()
377 OS << "};\n"; in EmitRegMappingTables()
379 OS << ";\n"; in EmitRegMappingTables()
384 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
387 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
391 OS << ";\n\n"; in EmitRegMappingTables()
409 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
410 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
411 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
413 OS << " = {\n"; in EmitRegMappingTables()
422 OS << " { " << getQualifiedName(I->first) << ", " << RegNo in EmitRegMappingTables()
425 OS << "};\n"; in EmitRegMappingTables()
427 OS << ";\n"; in EmitRegMappingTables()
432 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
435 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
438 OS << ";\n\n"; in EmitRegMappingTables()
444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
461 OS << " switch ("; in EmitRegMapping()
463 OS << "DwarfFlavour"; in EmitRegMapping()
465 OS << "EHFlavour"; in EmitRegMapping()
466 OS << ") {\n" in EmitRegMapping()
471 OS << " case " << i << ":\n"; in EmitRegMapping()
472 OS << " "; in EmitRegMapping()
474 OS << "RI->"; in EmitRegMapping()
479 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
481 OS << "false"; in EmitRegMapping()
483 OS << "true"; in EmitRegMapping()
484 OS << ");\n"; in EmitRegMapping()
485 OS << " break;\n"; in EmitRegMapping()
487 OS << " }\n"; in EmitRegMapping()
492 OS << " switch ("; in EmitRegMapping()
494 OS << "DwarfFlavour"; in EmitRegMapping()
496 OS << "EHFlavour"; in EmitRegMapping()
497 OS << ") {\n" in EmitRegMapping()
502 OS << " case " << i << ":\n"; in EmitRegMapping()
503 OS << " "; in EmitRegMapping()
505 OS << "RI->"; in EmitRegMapping()
510 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
512 OS << "false"; in EmitRegMapping()
514 OS << "true"; in EmitRegMapping()
515 OS << ");\n"; in EmitRegMapping()
516 OS << " break;\n"; in EmitRegMapping()
518 OS << " }\n"; in EmitRegMapping()
524 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
533 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
547 void print(raw_ostream &OS) { in print() argument
548 printBitVectorAsHex(OS, Values, 8); in print()
552 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
553 OS << getEnumName(VT); in printSimpleValueType()
556 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
557 OS << Idx->EnumValue; in printSubRegIndex()
600 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
601 OS << Val; in printDiff16()
604 static void printMask(raw_ostream &OS, unsigned Val) { in printMask() argument
605 OS << format("0x%08X", Val); in printMask()
628 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
632 OS << "unsigned " << ClName in emitComposeSubRegIndices()
667 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap[" in emitComposeSubRegIndices()
670 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
671 OS << "\n };\n"; in emitComposeSubRegIndices()
675 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1) in emitComposeSubRegIndices()
678 OS << " { "; in emitComposeSubRegIndices()
681 OS << Rows[r][i]->EnumValue << ", "; in emitComposeSubRegIndices()
683 OS << "0, "; in emitComposeSubRegIndices()
684 OS << "},\n"; in emitComposeSubRegIndices()
686 OS << " };\n\n"; in emitComposeSubRegIndices()
688 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" in emitComposeSubRegIndices()
691 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
693 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
694 OS << "}\n\n"; in emitComposeSubRegIndices()
698 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
738 OS << "unsigned " << ClName in emitComposeSubRegIndexLaneMask()
742 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
749 OS << " "; in emitComposeSubRegIndexLaneMask()
753 OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft); in emitComposeSubRegIndexLaneMask()
755 OS << "{ 0, 0 }"; in emitComposeSubRegIndexLaneMask()
757 OS << ", "; in emitComposeSubRegIndexLaneMask()
758 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
761 OS << " };\n" in emitComposeSubRegIndexLaneMask()
764 OS << " "; in emitComposeSubRegIndexLaneMask()
766 OS << format("&Seqs[%u]", Idx); in emitComposeSubRegIndexLaneMask()
768 OS << ","; in emitComposeSubRegIndexLaneMask()
769 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
771 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
773 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() in emitComposeSubRegIndexLaneMask()
790 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
792 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
794 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
795 OS << "#undef GET_REGINFO_MC_DESC\n"; in runMCDesc()
891 OS << "namespace llvm {\n\n"; in runMCDesc()
896 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
897 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
898 OS << "};\n\n"; in runMCDesc()
901 OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
902 LaneMaskSeqs.emit(OS, printMask, "~0u"); in runMCDesc()
903 OS << "};\n\n"; in runMCDesc()
906 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
907 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
908 OS << "};\n\n"; in runMCDesc()
911 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
913 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
915 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
918 OS << "};\n\n"; in runMCDesc()
922 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; in runMCDesc()
923 RegStrings.emit(OS, printChar); in runMCDesc()
924 OS << "};\n\n"; in runMCDesc()
926 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
928 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
933 OS << " { " << RegStrings.get(Reg.getName()) << ", " in runMCDesc()
940 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
944 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
949 OS << " { " << getQualifiedName(Roots.front()->TheDef); in runMCDesc()
951 OS << ", " << getQualifiedName(Roots[r]->TheDef); in runMCDesc()
952 OS << " },\n"; in runMCDesc()
954 OS << "};\n\n"; in runMCDesc()
959 OS << "namespace { // Register classes...\n"; in runMCDesc()
973 OS << " // " << Name << " Register Class...\n" in runMCDesc()
978 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
980 OS << "\n };\n\n"; in runMCDesc()
982 OS << " // " << Name << " Bit set.\n" in runMCDesc()
990 BVE.print(OS); in runMCDesc()
991 OS << "\n };\n\n"; in runMCDesc()
994 OS << "}\n\n"; in runMCDesc()
997 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; in runMCDesc()
998 RegClassStrings.emit(OS, printChar); in runMCDesc()
999 OS << "};\n\n"; in runMCDesc()
1001 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1011 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1021 OS << "};\n\n"; in runMCDesc()
1023 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1026 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1027 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1029 OS << " 0,\n"; in runMCDesc()
1038 OS << " " << Value << ",\n"; in runMCDesc()
1040 OS << "};\n"; // End of HW encoding table in runMCDesc()
1043 OS << "static inline void Init" << TargetName in runMCDesc()
1057 EmitRegMapping(OS, Regs, false); in runMCDesc()
1059 OS << "}\n\n"; in runMCDesc()
1061 OS << "} // End llvm namespace\n"; in runMCDesc()
1062 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1066 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1068 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1070 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1071 OS << "#undef GET_REGINFO_HEADER\n"; in runTargetHeader()
1076 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1078 OS << "namespace llvm {\n\n"; in runTargetHeader()
1080 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1086 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1093 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1108 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1115 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1117 OS << "} // end of namespace " << TargetName << "\n\n"; in runTargetHeader()
1119 OS << "} // End llvm namespace\n"; in runTargetHeader()
1120 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1127 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1129 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1131 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1132 OS << "#undef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1134 OS << "namespace llvm {\n\n"; in runTargetDesc()
1137 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1160 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1161 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1162 OS << "};\n"; in runTargetDesc()
1165 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; in runTargetDesc()
1168 OS << Idx.getName(); in runTargetDesc()
1169 OS << "\", \""; in runTargetDesc()
1171 OS << "\" };\n\n"; in runTargetDesc()
1174 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; in runTargetDesc()
1176 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n'; in runTargetDesc()
1178 OS << " };\n\n"; in runTargetDesc()
1180 OS << "\n"; in runTargetDesc()
1184 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1212 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1213 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1224 OS << "\n "; in runTargetDesc()
1225 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1226 OS << "// " << Idx.getName(); in runTargetDesc()
1229 OS << "\n};\n\n"; in runTargetDesc()
1232 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1234 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1235 OS << "};\n\n"; in runTargetDesc()
1245 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1248 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1249 OS << " nullptr\n};\n\n"; in runTargetDesc()
1255 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1263 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1265 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1266 OS << " };\n"; in runTargetDesc()
1269 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1275 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1277 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1278 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1285 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1289 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1297 OS << "NullRegClasses,\n "; in runTargetDesc()
1299 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1301 OS << "nullptr\n"; in runTargetDesc()
1303 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1304 OS << " };\n\n"; in runTargetDesc()
1307 OS << "}\n"; in runTargetDesc()
1310 OS << "\nnamespace {\n"; in runTargetDesc()
1311 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
1313 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1314 OS << " };\n"; in runTargetDesc()
1315 OS << "}\n"; // End of anonymous namespace... in runTargetDesc()
1319 OS << "\nstatic const TargetRegisterInfoDesc " in runTargetDesc()
1321 OS << " { 0, 0 },\n"; in runTargetDesc()
1325 OS << " { "; in runTargetDesc()
1326 OS << Reg.CostPerUse << ", " in runTargetDesc()
1329 OS << "};\n"; // End of register descriptors... in runTargetDesc()
1338 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1339 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1344 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1350 OS << " static const uint8_t Table["; in runTargetDesc()
1352 OS << " static const uint16_t Table["; in runTargetDesc()
1355 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1357 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1360 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1363 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1365 OS << " },\n"; in runTargetDesc()
1367 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1374 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1377 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1378 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1379 OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1380 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1381 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1382 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1383 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1384 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1386 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1388 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1390 OS << ClassName << "::\n" << ClassName in runTargetDesc()
1395 OS.write_hex(RegBank.CoveringLanes); in runTargetDesc()
1396 OS << ") {\n" in runTargetDesc()
1411 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1413 OS << "}\n\n"; in runTargetDesc()
1425 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1428 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1429 OS << "0 };\n"; in runTargetDesc()
1444 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1446 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1447 OS << "};\n"; in runTargetDesc()
1449 OS << "\n\n"; in runTargetDesc()
1451 OS << "} // End llvm namespace\n"; in runTargetDesc()
1452 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1455 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1460 runEnums(OS, Target, RegBank); in run()
1461 runMCDesc(OS, Target, RegBank); in run()
1462 runTargetHeader(OS, Target, RegBank); in run()
1463 runTargetDesc(OS, Target, RegBank); in run()
1468 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1469 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()