75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
80 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
85 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
88 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
91 static DecodeStatus Decode2RInstruction(MCInst &Inst,
96 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
101 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
106 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
111 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
116 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
121 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
126 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
131 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
136 static DecodeStatus Decode3RInstruction(MCInst &Inst,
141 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
146 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
151 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
156 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
161 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
166 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
171 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
176 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
181 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
186 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
191 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
198 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,  in DecodeGRRegsRegisterClass()  argument
206   Inst.addOperand(MCOperand::createReg(Reg));  in DecodeGRRegsRegisterClass()
210 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,  in DecodeRRegsRegisterClass()  argument
218   Inst.addOperand(MCOperand::createReg(Reg));  in DecodeRRegsRegisterClass()
222 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,  in DecodeBitpOperand()  argument
229   Inst.addOperand(MCOperand::createImm(Values[Val]));  in DecodeBitpOperand()
233 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,  in DecodeNegImmOperand()  argument
235   Inst.addOperand(MCOperand::createImm(-(int64_t)Val));  in DecodeNegImmOperand()
274 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2OpInstructionFail()  argument
280     Inst.setOpcode(XCore::STW_2rus);  in Decode2OpInstructionFail()
281     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
283     Inst.setOpcode(XCore::LDW_2rus);  in Decode2OpInstructionFail()
284     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
286     Inst.setOpcode(XCore::ADD_3r);  in Decode2OpInstructionFail()
287     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
289     Inst.setOpcode(XCore::SUB_3r);  in Decode2OpInstructionFail()
290     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
292     Inst.setOpcode(XCore::SHL_3r);  in Decode2OpInstructionFail()
293     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
295     Inst.setOpcode(XCore::SHR_3r);  in Decode2OpInstructionFail()
296     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
298     Inst.setOpcode(XCore::EQ_3r);  in Decode2OpInstructionFail()
299     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
301     Inst.setOpcode(XCore::AND_3r);  in Decode2OpInstructionFail()
302     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
304     Inst.setOpcode(XCore::OR_3r);  in Decode2OpInstructionFail()
305     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
307     Inst.setOpcode(XCore::LDW_3r);  in Decode2OpInstructionFail()
308     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
310     Inst.setOpcode(XCore::LD16S_3r);  in Decode2OpInstructionFail()
311     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
313     Inst.setOpcode(XCore::LD8U_3r);  in Decode2OpInstructionFail()
314     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
316     Inst.setOpcode(XCore::ADD_2rus);  in Decode2OpInstructionFail()
317     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
319     Inst.setOpcode(XCore::SUB_2rus);  in Decode2OpInstructionFail()
320     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
322     Inst.setOpcode(XCore::SHL_2rus);  in Decode2OpInstructionFail()
323     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
325     Inst.setOpcode(XCore::SHR_2rus);  in Decode2OpInstructionFail()
326     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
328     Inst.setOpcode(XCore::EQ_2rus);  in Decode2OpInstructionFail()
329     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
331     Inst.setOpcode(XCore::TSETR_3r);  in Decode2OpInstructionFail()
332     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
334     Inst.setOpcode(XCore::LSS_3r);  in Decode2OpInstructionFail()
335     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
337     Inst.setOpcode(XCore::LSU_3r);  in Decode2OpInstructionFail()
338     return Decode3RInstruction(Inst, Insn, Address, Decoder);  in Decode2OpInstructionFail()
344 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2RInstruction()  argument
349     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in Decode2RInstruction()
351   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode2RInstruction()
352   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode2RInstruction()
357 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2RImmInstruction()  argument
362     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in Decode2RImmInstruction()
364   Inst.addOperand(MCOperand::createImm(Op1));  in Decode2RImmInstruction()
365   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode2RImmInstruction()
370 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeR2RInstruction()  argument
375     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeR2RInstruction()
377   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeR2RInstruction()
378   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeR2RInstruction()
383 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2RSrcDstInstruction()  argument
388     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in Decode2RSrcDstInstruction()
390   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode2RSrcDstInstruction()
391   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode2RSrcDstInstruction()
392   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode2RSrcDstInstruction()
397 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeRUSInstruction()  argument
402     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeRUSInstruction()
404   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeRUSInstruction()
405   Inst.addOperand(MCOperand::createImm(Op2));  in DecodeRUSInstruction()
410 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeRUSBitpInstruction()  argument
415     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeRUSBitpInstruction()
417   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeRUSBitpInstruction()
418   DecodeBitpOperand(Inst, Op2, Address, Decoder);  in DecodeRUSBitpInstruction()
423 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeRUSSrcDstBitpInstruction()  argument
428     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeRUSSrcDstBitpInstruction()
430   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeRUSSrcDstBitpInstruction()
431   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeRUSSrcDstBitpInstruction()
432   DecodeBitpOperand(Inst, Op2, Address, Decoder);  in DecodeRUSSrcDstBitpInstruction()
437 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL2OpInstructionFail()  argument
444     Inst.setOpcode(XCore::STW_l3r);  in DecodeL2OpInstructionFail()
445     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
447     Inst.setOpcode(XCore::XOR_l3r);  in DecodeL2OpInstructionFail()
448     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
450     Inst.setOpcode(XCore::ASHR_l3r);  in DecodeL2OpInstructionFail()
451     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
453     Inst.setOpcode(XCore::LDAWF_l3r);  in DecodeL2OpInstructionFail()
454     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
456     Inst.setOpcode(XCore::LDAWB_l3r);  in DecodeL2OpInstructionFail()
457     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
459     Inst.setOpcode(XCore::LDA16F_l3r);  in DecodeL2OpInstructionFail()
460     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
462     Inst.setOpcode(XCore::LDA16B_l3r);  in DecodeL2OpInstructionFail()
463     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
465     Inst.setOpcode(XCore::MUL_l3r);  in DecodeL2OpInstructionFail()
466     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
468     Inst.setOpcode(XCore::DIVS_l3r);  in DecodeL2OpInstructionFail()
469     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
471     Inst.setOpcode(XCore::DIVU_l3r);  in DecodeL2OpInstructionFail()
472     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
474     Inst.setOpcode(XCore::ST16_l3r);  in DecodeL2OpInstructionFail()
475     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
477     Inst.setOpcode(XCore::ST8_l3r);  in DecodeL2OpInstructionFail()
478     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
480     Inst.setOpcode(XCore::ASHR_l2rus);  in DecodeL2OpInstructionFail()
481     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
483     Inst.setOpcode(XCore::OUTPW_l2rus);  in DecodeL2OpInstructionFail()
484     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
486     Inst.setOpcode(XCore::INPW_l2rus);  in DecodeL2OpInstructionFail()
487     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
489     Inst.setOpcode(XCore::LDAWF_l2rus);  in DecodeL2OpInstructionFail()
490     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
492     Inst.setOpcode(XCore::LDAWB_l2rus);  in DecodeL2OpInstructionFail()
493     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
495     Inst.setOpcode(XCore::CRC_l3r);  in DecodeL2OpInstructionFail()
496     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
498     Inst.setOpcode(XCore::REMS_l3r);  in DecodeL2OpInstructionFail()
499     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
501     Inst.setOpcode(XCore::REMU_l3r);  in DecodeL2OpInstructionFail()
502     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);  in DecodeL2OpInstructionFail()
508 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL2RInstruction()  argument
514     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeL2RInstruction()
516   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL2RInstruction()
517   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL2RInstruction()
522 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeLR2RInstruction()  argument
528     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);  in DecodeLR2RInstruction()
530   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeLR2RInstruction()
531   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeLR2RInstruction()
536 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode3RInstruction()  argument
541     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode3RInstruction()
542     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode3RInstruction()
543     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in Decode3RInstruction()
549 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode3RImmInstruction()  argument
554     Inst.addOperand(MCOperand::createImm(Op1));  in Decode3RImmInstruction()
555     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode3RImmInstruction()
556     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in Decode3RImmInstruction()
562 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2RUSInstruction()  argument
567     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode2RUSInstruction()
568     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode2RUSInstruction()
569     Inst.addOperand(MCOperand::createImm(Op3));  in Decode2RUSInstruction()
575 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in Decode2RUSBitpInstruction()  argument
580     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in Decode2RUSBitpInstruction()
581     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in Decode2RUSBitpInstruction()
582     DecodeBitpOperand(Inst, Op3, Address, Decoder);  in Decode2RUSBitpInstruction()
588 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL3RInstruction()  argument
594     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL3RInstruction()
595     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL3RInstruction()
596     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL3RInstruction()
602 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL3RSrcDstInstruction()  argument
608     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL3RSrcDstInstruction()
609     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL3RSrcDstInstruction()
610     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL3RSrcDstInstruction()
611     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL3RSrcDstInstruction()
617 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL2RUSInstruction()  argument
623     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL2RUSInstruction()
624     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL2RUSInstruction()
625     Inst.addOperand(MCOperand::createImm(Op3));  in DecodeL2RUSInstruction()
631 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL2RUSBitpInstruction()  argument
637     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL2RUSBitpInstruction()
638     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL2RUSBitpInstruction()
639     DecodeBitpOperand(Inst, Op3, Address, Decoder);  in DecodeL2RUSBitpInstruction()
645 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL6RInstruction()  argument
655   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL6RInstruction()
656   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL6RInstruction()
657   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL6RInstruction()
658   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL6RInstruction()
659   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);  in DecodeL6RInstruction()
660   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);  in DecodeL6RInstruction()
665 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL5RInstructionFail()  argument
668   Inst.clear();  in DecodeL5RInstructionFail()
672     Inst.setOpcode(XCore::LMUL_l6r);  in DecodeL5RInstructionFail()
673     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);  in DecodeL5RInstructionFail()
679 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL5RInstruction()  argument
685     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);  in DecodeL5RInstruction()
688     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);  in DecodeL5RInstruction()
690   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL5RInstruction()
691   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL5RInstruction()
692   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL5RInstruction()
693   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL5RInstruction()
694   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);  in DecodeL5RInstruction()
699 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL4RSrcDstInstruction()  argument
706     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL4RSrcDstInstruction()
707     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL4RSrcDstInstruction()
710     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL4RSrcDstInstruction()
711     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL4RSrcDstInstruction()
712     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL4RSrcDstInstruction()
718 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,  in DecodeL4RSrcDstSrcDstInstruction()  argument
725     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()
726     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()
729     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()
730     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()
731     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()
732     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);  in DecodeL4RSrcDstSrcDstInstruction()