Lines Matching refs:U
42 #define U(num) num macro
44 #define U(num) num ## U macro
46 #define U(num) num/**/U macro
49 #define PROM_ADDR U(0x41000000) /* PROM */
50 #define PROM_SPACE U(0x00040000)
51 #define NVRAM_ADDR U(0x45000000) /* Non Volatile */
52 #define NVRAM_SPACE U(0x00001FDC)
53 #define FUSE_ROM_ADDR U(0x43000000) /* FUSE_ROM */
55 #define OBIO_CLOCK_BASE U(0x45000000) /* Mostek or Dallas TimeKeeper */
56 #define OBIO_PIO0_BASE U(0x49000000) /* PIO-0 */
57 #define OBIO_PIO0_SPACE U(0x00000004)
58 #define OBIO_PIO0A U(0x49000000) /* PIO-0 port A */
59 #define OBIO_PIO0B U(0x49000001) /* PIO-0 port B */
60 #define OBIO_PIO0C U(0x49000002) /* PIO-0 port C*/
61 #define OBIO_PIO0 U(0x49000003) /* PIO-0 control */
62 #define OBIO_PIO1_BASE U(0x4D000000) /* PIO-1 */
63 #define OBIO_PIO1_SPACE U(0x00000004)
64 #define OBIO_PIO1A U(0x4D000000) /* PIO-1 port A */
65 #define OBIO_PIO1B U(0x4D000001) /* PIO-1 port B */
66 #define OBIO_PIO1C U(0x4D000002) /* PIO-1 port C*/
67 #define OBIO_PIO1 U(0x4D000003) /* PIO-1 control */
68 #define OBIO_SIO U(0x51000000) /* SIO */
69 #define OBIO_TAS U(0x61000000) /* TAS register */
70 #define OBIO_CLOCK U(0x63000000) /* system clock */
72 #define TRI_PORT_RAM U(0x71000000) /* 3 port RAM */
74 #define EXT_A_ADDR U(0x81000000) /* extension board A */
75 #define EXT_A_SPACE U(0x02000000)
76 #define EXT_B_ADDR U(0x83000000) /* extension board B */
77 #define EXT_B_SPACE U(0x01000000)
78 #define PC_BASE U(0x90000000) /* pc-98 extension board */
79 #define PC_SPACE U(0x02000000)
81 #define MROM_ADDR U(0xA1000000) /* Mask ROM address */
83 #define BMAP_START U(0xB1000000) /* Bitmap start address */
85 #define BMAP_RFCNT U(0xB1000000) /* RFCNT register */
86 #define BMAP_BMSEL U(0xB1040000) /* BMSEL register */
87 #define BMAP_BMP U(0xB1080000) /* common bitmap plane */
88 #define BMAP_BMAP0 U(0xB10C0000) /* bitmap plane 0 */
89 #define BMAP_BMAP1 U(0xB1100000) /* bitmap plane 1 */
90 #define BMAP_BMAP2 U(0xB1140000) /* bitmap plane 2 */
91 #define BMAP_BMAP3 U(0xB1180000) /* bitmap plane 3 */
92 #define BMAP_BMAP4 U(0xB11C0000) /* bitmap plane 4 */
93 #define BMAP_BMAP5 U(0xB1200000) /* bitmap plane 5 */
94 #define BMAP_BMAP6 U(0xB1240000) /* bitmap plane 6 */
95 #define BMAP_BMAP7 U(0xB1280000) /* bitmap plane 7 */
96 #define BMAP_FN U(0xB12C0000) /* common bitmap function */
97 #define BMAP_FN0 U(0xB1300000) /* bitmap function 0 */
98 #define BMAP_FN1 U(0xB1340000) /* bitmap function 1 */
99 #define BMAP_FN2 U(0xB1380000) /* bitmap function 2 */
100 #define BMAP_FN3 U(0xB13C0000) /* bitmap function 3 */
101 #define BMAP_FN4 U(0xB1400000) /* bitmap function 4 */
102 #define BMAP_FN5 U(0xB1440000) /* bitmap function 5 */
103 #define BMAP_FN6 U(0xB1480000) /* bitmap function 6 */
104 #define BMAP_FN7 U(0xB14C0000) /* bitmap function 7 */
105 #define BMAP_END U(0xB1500000)
106 #define BMAP_END24P U(0xB1800000) /* end of 24p framemem */
107 #define BMAP_PALLET0 U(0xC0000000) /* color pallet */
108 #define BMAP_PALLET1 U(0xC1000000) /* color pallet */
109 #define BMAP_PALLET2 U(0xC1100000) /* color pallet */
110 #define BOARD_CHECK_REG U(0xD0000000) /* board check register */
111 #define BMAP_CRTC U(0xD1000000) /* CRTC-II */
112 #define BMAP_IDENTROM U(0xD1800000) /* bitmap-board identify ROM */
113 #define SCSI_ADDR U(0xE1000000) /* SCSI address */
114 #define SCSI_2_ADDR U(0xE1000040) /* 2nd SCSI address */
115 #define LANCE_ADDR U(0xF1000000) /* LANCE */