Lines Matching refs:a2

30     movi    a2, 0x12345678
31     wsr     a2, ccount
34     sub     a3, a3, a2
64     movi    a2, 0
65     wsr     a2, intenable
66     rsr     a2, interrupt
67     wsr     a2, intclear
68     movi    a2, 0
70     wsr     a2, ccompare1
73     wsr     a2, ccompare2
75     movi    a2, 0x12345678
76     wsr     a2, ccompare0
79     movi    a2, 0x12345677
80     wsr     a2, ccount
83     rsr     a2, interrupt
85     assert  eq, a2, a3
89     movi    a2, 0
90     wsr     a2, intenable
91     rsr     a2, interrupt
92     wsr     a2, intclear
93     movi    a2, 0
95     wsr     a2, ccompare1
98     wsr     a2, ccompare2
101     make_ccount_delta a2, a15
102     wsr     a2, ccompare0
107     sub     a4, a4, a2
117     movi    a2, 0
118     wsr     a2, intenable
119     rsr     a2, interrupt
120     wsr     a2, intclear
121     movi    a2, 0
123     wsr     a2, ccompare1
126     wsr     a2, ccompare2
130     make_ccount_delta a2, a15
131     wsr     a2, ccompare0
133     rsr     a2, interrupt
134     assert  eqi, a2, 0
136     movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
137     wsr     a2, intenable
138     rsil    a2, 0
145     rsr     a2, exccause
146     assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
154     movi    a2, 0
155     wsr     a2, intenable
156     rsr     a2, interrupt
157     wsr     a2, intclear
158     movi    a2, 0
159     wsr     a2, ccompare0
161     wsr     a2, ccompare2
165     make_ccount_delta a2, a15
166     wsr     a2, ccompare1
168     rsr     a2, interrupt
169     assert  eqi, a2, 0
170     movi    a2, 1 << XCHAL_TIMER1_INTERRUPT
171     wsr     a2, intenable
172     rsil    a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
179     rsr     a2, exccause
180     assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
189     movi    a2, 0
190     wsr     a2, intenable
191     rsr     a2, interrupt
192     wsr     a2, intclear
193     movi    a2, 0
194     wsr     a2, ccompare0
195     wsr     a2, ccompare1
198     make_ccount_delta a2, a15
199     wsr     a2, ccompare2
201     rsr     a2, interrupt
202     assert  eqi, a2, 0
203     movi    a2, 1 << XCHAL_TIMER2_INTERRUPT
204     wsr     a2, intenable
205     rsil    a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
212     rsr     a2, exccause
213     assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
221     movi    a2, 0
222     wsr     a2, intenable
223     rsr     a2, interrupt
224     wsr     a2, intclear
225     movi    a2, 0
227     wsr     a2, ccompare2
231     make_ccount_delta a2, a15
233     wsr     a2, ccompare1
235     add     a2, a2, a15
236     wsr     a2, ccompare0
238     rsr     a2, interrupt
239     assert  eqi, a2, 0
241     movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
242     wsr     a2, intenable
243     rsil    a2, 0
251     rsr     a2, exccause
252     assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
258     movi    a2, 0
259     wsr     a2, intenable
260     rsr     a2, interrupt
261     wsr     a2, intclear
262     movi    a2, 0
264     wsr     a2, ccompare2
267     make_ccount_delta a2, a15
269     wsr     a2, ccompare1
271     add     a2, a2, a15
272     wsr     a2, ccompare0
274     rsr     a2, interrupt
275     assert  eqi, a2, 0
277     movi    a2, 1 << XCHAL_TIMER0_INTERRUPT
278     wsr     a2, intenable
283     rsr     a2, exccause
284     assert  eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */