// DESCRIPTION: Verilator: Verilog Test module // Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 // // stream pack/unpack for integer_type only // slice_size ::= simple_type | constant_expression // simple_type ::= // integer_type | non_integer_type | ps_type_identifier | ps_parameter_identifier // non_integer_type ::= shortreal | real | realtime // integer_type ::= // integer_vector_type | integer_atom_type // integer_atom_type ::= byte | shortint | int | longint | integer | time // integer_vector_type ::= bit | logic | reg // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2020 by Victor Besyakov. // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs clk ); input clk; logic [31:0] packed_data_32; logic [31:0] packed_data_32_ref; logic [31:0] v_packed_data_32; logic [31:0] v_packed_data_32_ref; logic [63:0] packed_data_64; logic [63:0] packed_data_64_ref; logic [63:0] v_packed_data_64; logic [63:0] v_packed_data_64_ref; logic [127:0] packed_data_128; logic [127:0] packed_data_128_ref; logic [127:0] v_packed_data_128; logic [127:0] v_packed_data_128_ref; logic [127:0] packed_data_128_i; logic [127:0] packed_data_128_i_ref; logic [255:0] packed_data_256; logic [255:0] packed_data_256_ref; logic [255:0] packed_time_256; logic [255:0] packed_time_256_ref; // //integer_atom_type // byte byte_in[4]; byte byte_out[4]; // int int_in[4]; int int_out[4]; // // shortint shortint_in[4]; shortint shortint_out[4]; // longint longint_in[4]; longint longint_out[4]; // integer integer_in[4]; integer integer_out[4]; // time time_in[4]; time time_out[4]; //integer_vector_type typedef bit [7:0] test_byte; typedef bit [15:0] test_short; typedef bit [31:0] test_word; typedef bit [63:0] test_long; // test_byte bit_in[4]; test_byte bit_out[4]; // test_short logic_in[4]; test_short logic_out[4]; // test_word reg_in[4]; test_word reg_out[4]; // string error = ""; initial begin //init $write("*-* START t_stream_pack_unpack *-*\n"); error = test_integer_type_1(error); `ifdef TEST_VERBOSE print_all_data("test_integer_type_1"); `endif error = test_integer_type_2(error); `ifdef TEST_VERBOSE print_all_data("test_integer_type_2"); `endif // if (error == "") $write("*-* All Finished *-*\n"); else begin $write("*-* TEST failed error %s *-*:\n", error); print_data_error(error); end $finish; end // initial begin function string test_integer_type_1(string error); automatic string error_; automatic string function_name_ = "test_integer_type_1"; error_ = error; if (error_ == "") begin clean_packed_data (); init_data(); //pack packed_data_32 = {<<8{byte_in}}; packed_data_64 = {<<16{shortint_in}}; packed_data_128 = {<<32{int_in}}; packed_data_128_i = {<<32{integer_in}}; packed_data_256 = {<<64{longint_in}}; packed_time_256 = {<<64{time_in}}; v_packed_data_32 = {<<8{bit_in}}; v_packed_data_64 = {<<16{logic_in}}; v_packed_data_128 = {<<32{reg_in}}; //unpack {<<8{byte_out}} = packed_data_32; {<<16{shortint_out}} = packed_data_64; {<<32{int_out}} = packed_data_128; {<<32{integer_out}} = packed_data_128_i; {<<64{longint_out}} = packed_data_256; {<<64{time_out}} = packed_time_256; {<<8{bit_out}} = v_packed_data_32; {<<16{logic_out}} = v_packed_data_64; {<<32{reg_out}} = v_packed_data_128; error_ = comp_in_out(); end // if (error == "") return error_; endfunction : test_integer_type_1 function string test_integer_type_2(string error); automatic string error_; automatic string function_name_ = "test_integer_type_2"; error_ = error; if (error_ == "") begin clean_packed_data (); init_data(); //pack packed_data_32 = {<