; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vadc.nxv1i8.nxv1i8( , , , i32); define @intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i8.nxv1i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i8.nxv2i8( , , , i32); define @intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i8.nxv2i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i8.nxv4i8( , , , i32); define @intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i8.nxv4i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i8.nxv8i8( , , , i32); define @intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i8.nxv8i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i8.nxv16i8( , , , i32); define @intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i8.nxv16i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv32i8.nxv32i8( , , , i32); define @intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i8.nxv32i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv64i8.nxv64i8( , , , i32); define @intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv64i8.nxv64i8( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i16.nxv1i16( , , , i32); define @intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i16.nxv1i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i16.nxv2i16( , , , i32); define @intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i16.nxv2i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i16.nxv4i16( , , , i32); define @intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i16.nxv4i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i16.nxv8i16( , , , i32); define @intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i16.nxv8i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i16.nxv16i16( , , , i32); define @intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i16.nxv16i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv32i16.nxv32i16( , , , i32); define @intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i16.nxv32i16( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i32.nxv1i32( , , , i32); define @intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i32.nxv1i32( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i32.nxv2i32( , , , i32); define @intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i32.nxv2i32( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i32.nxv4i32( , , , i32); define @intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i32.nxv4i32( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i32.nxv8i32( , , , i32); define @intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i32.nxv8i32( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i32.nxv16i32( , , , i32); define @intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i32.nxv16i32( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i64.nxv1i64( , , , i32); define @intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i64.nxv1i64( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i64.nxv2i64( , , , i32); define @intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i64.nxv2i64( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i64.nxv4i64( , , , i32); define @intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i64.nxv4i64( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i64.nxv8i64( , , , i32); define @intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i64.nxv8i64( %0, %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv32i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv64i8.i8( , i8, , i32); define @intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv32i16.i16( , i16, , i32); define @intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i32.i32( , i32, , i32); define @intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i32.i32( , i32, , i32); define @intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i32.i32( , i32, , i32); define @intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i32.i32( , i32, , i32); define @intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv16i32.i32( , i32, , i32); define @intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv1i64.i64( , i64, , i32); define @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64( %0, i64 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: vlse64.v v25, (a0), zero ; CHECK-NEXT: vadc.vvm v8, v8, v25, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i64.i64( %0, i64 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv2i64.i64( , i64, , i32); define @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64( %0, i64 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: vlse64.v v26, (a0), zero ; CHECK-NEXT: vadc.vvm v8, v8, v26, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i64.i64( %0, i64 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv4i64.i64( , i64, , i32); define @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64( %0, i64 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: vlse64.v v28, (a0), zero ; CHECK-NEXT: vadc.vvm v8, v8, v28, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i64.i64( %0, i64 %1, %2, i32 %3) ret %a } declare @llvm.riscv.vadc.nxv8i64.i64( , i64, , i32); define @intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64( %0, i64 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i64.i64( %0, i64 %1, %2, i32 %3) ret %a } define @intrinsic_vadc_vim_nxv1i8_nxv1i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv2i8_nxv2i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv4i8_nxv4i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv8i8_nxv8i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv16i8_nxv16i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv32i8_nxv32i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv64i8_nxv64i8_i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv1i16_nxv1i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv2i16_nxv2i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv4i16_nxv4i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv8i16_nxv8i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv16i16_nxv16i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv32i16_nxv32i16_i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv1i32_nxv1i32_i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv2i32_nxv2i32_i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv4i32_nxv4i32_i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv8i32_nxv8i32_i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv16i32_nxv16i32_i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv1i64_nxv1i64_i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv1i64.i64( %0, i64 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv2i64_nxv2i64_i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv2i64.i64( %0, i64 -9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv4i64_nxv4i64_i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, 9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv4i64.i64( %0, i64 9, %1, i32 %2) ret %a } define @intrinsic_vadc_vim_nxv8i64_nxv8i64_i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vadc_vim_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vadc.vim v8, v8, -9, v0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vadc.nxv8i64.i64( %0, i64 -9, %1, i32 %2) ret %a }