// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*- // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// /// \file /// WebAssembly Memory operand code-gen constructs. /// //===----------------------------------------------------------------------===// // TODO: // - WebAssemblyTargetLowering having to do with atomics // - Each has optional alignment. // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16 // local types. These memory-only types instead zero- or sign-extend into local // types when loading, and truncate when storing. // Address Operands // These patterns match the static (offset) and dynamic (address stack operand) // operands for loads and stores, based on a combination of target global // addresses and constants. // For example, // (load (add tga, x)) -> load offset=tga, addr=x // (store v, tga) -> store v, offset=tga, addr=0 // (load (add const, x)) -> load offset=const, addr=x // (store v, const) -> store v, offset=const, addr=0 // (load x) -> load offset=0, addr=x def AddrOps32 : ComplexPattern; def AddrOps64 : ComplexPattern; // Defines atomic and non-atomic loads, regular and extending. multiclass WebAssemblyLoad reqs = []> { let mayLoad = 1, UseNamedOperandTable = 1 in { defm "_A32": I<(outs rc:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), (outs), (ins P2Align:$p2align, offset32_op:$off), [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"), !strconcat(Name, "\t${off}${p2align}"), Opcode, false>, Requires; defm "_A64": I<(outs rc:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr), (outs), (ins P2Align:$p2align, offset64_op:$off), [], !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}"), !strconcat(Name, "\t${off}${p2align}"), Opcode, true>, Requires; } } // Basic load. // FIXME: When we can break syntax compatibility, reorder the fields in the // asmstrings to match the binary encoding. defm LOAD_I32 : WebAssemblyLoad; defm LOAD_I64 : WebAssemblyLoad; defm LOAD_F32 : WebAssemblyLoad; defm LOAD_F64 : WebAssemblyLoad; // Extending load. defm LOAD8_S_I32 : WebAssemblyLoad; defm LOAD8_U_I32 : WebAssemblyLoad; defm LOAD16_S_I32 : WebAssemblyLoad; defm LOAD16_U_I32 : WebAssemblyLoad; defm LOAD8_S_I64 : WebAssemblyLoad; defm LOAD8_U_I64 : WebAssemblyLoad; defm LOAD16_S_I64 : WebAssemblyLoad; defm LOAD16_U_I64 : WebAssemblyLoad; defm LOAD32_S_I64 : WebAssemblyLoad; defm LOAD32_U_I64 : WebAssemblyLoad; // Pattern matching multiclass LoadPat { def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr))), (!cast(Name # "_A32") 0, offset32_op:$offset, I32:$addr)>, Requires<[HasAddr32]>; def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr))), (!cast(Name # "_A64") 0, offset64_op:$offset, I64:$addr)>, Requires<[HasAddr64]>; } defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; defm : LoadPat; // Defines atomic and non-atomic stores, regular and truncating multiclass WebAssemblyStore reqs = []> { let mayStore = 1, UseNamedOperandTable = 1 in defm "_A32" : I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val), (outs), (ins P2Align:$p2align, offset32_op:$off), [], !strconcat(Name, "\t${off}(${addr})${p2align}, $val"), !strconcat(Name, "\t${off}${p2align}"), Opcode, false>, Requires; let mayStore = 1, UseNamedOperandTable = 1 in defm "_A64" : I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, rc:$val), (outs), (ins P2Align:$p2align, offset64_op:$off), [], !strconcat(Name, "\t${off}(${addr})${p2align}, $val"), !strconcat(Name, "\t${off}${p2align}"), Opcode, true>, Requires; } // Basic store. // Note: WebAssembly inverts SelectionDAG's usual operand order. defm STORE_I32 : WebAssemblyStore; defm STORE_I64 : WebAssemblyStore; defm STORE_F32 : WebAssemblyStore; defm STORE_F64 : WebAssemblyStore; multiclass StorePat { def : Pat<(kind ty:$val, (AddrOps32 offset32_op:$offset, I32:$addr)), (!cast(Name # "_A32") 0, offset32_op:$offset, I32:$addr, ty:$val)>, Requires<[HasAddr32]>; def : Pat<(kind ty:$val, (AddrOps64 offset64_op:$offset, I64:$addr)), (!cast(Name # "_A64") 0, offset64_op:$offset, I64:$addr, ty:$val)>, Requires<[HasAddr64]>; } defm : StorePat; defm : StorePat; defm : StorePat; defm : StorePat; // Truncating store. defm STORE8_I32 : WebAssemblyStore; defm STORE16_I32 : WebAssemblyStore; defm STORE8_I64 : WebAssemblyStore; defm STORE16_I64 : WebAssemblyStore; defm STORE32_I64 : WebAssemblyStore; defm : StorePat; defm : StorePat; defm : StorePat; defm : StorePat; defm : StorePat; multiclass MemoryOps { // Current memory size. defm MEMORY_SIZE_A#B : I<(outs rc:$dst), (ins i32imm:$flags), (outs), (ins i32imm:$flags), [(set rc:$dst, (int_wasm_memory_size (i32 imm:$flags)))], "memory.size\t$dst, $flags", "memory.size\t$flags", 0x3f>; // Grow memory. defm MEMORY_GROW_A#B : I<(outs rc:$dst), (ins i32imm:$flags, rc:$delta), (outs), (ins i32imm:$flags), [(set rc:$dst, (int_wasm_memory_grow (i32 imm:$flags), rc:$delta))], "memory.grow\t$dst, $flags, $delta", "memory.grow\t$flags", 0x40>; } defm : MemoryOps; defm : MemoryOps;