| /dports/lang/mit-scheme/mit-scheme-9.2/src/edwin/ |
| H A D | verilog.scm | 36 (define-major-mode verilog fundamental "Verilog" unknown
76 (define-key 'verilog #\linefeed 'reindent-then-newline-and-indent) unknown
77 (define-key 'verilog #\rubout 'backward-delete-char-untabify) unknown
78 (define-key 'verilog #\tab 'keyparser-indent-line) unknown
79 (define-key 'verilog #\c-m-\\ 'keyparser-indent-region) unknown
80 (define-key 'verilog #\) 'lisp-insert-paren) unknown
81 (define-key 'verilog #\] 'lisp-insert-paren) unknown
82 (define-key 'verilog #\} 'lisp-insert-paren) unknown
83 (define-key 'verilog #\m-tab 'complete-keyword) unknown
|
| H A D | loadef.scm | 257 (define-autoload-major-mode 'verilog 'fundamental "Verilog" 'VERILOG-MODE unknown
|
| /dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/examples/ |
| H A D | Makefile.am | 1 SUBDIRS = vams switcap verilog analog spice-noqsi subdir
|
| /dports/misc/tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/ |
| H A D | Makefile | 35 verilog: target
|
| /dports/misc/py-tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/ |
| H A D | Makefile | 35 verilog: target
|
| /dports/cad/opentimer/OpenTimer-18d28ff/main/tau18/ |
| H A D | tau18.cpp | 18 std::filesystem::path verilog; in main() local
|
| /dports/misc/tvm/incubator-tvm-0.6.1/vta/apps/gemm/hardware/chisel/ |
| H A D | Makefile | 104 verilog: $(chisel_build_dir)/$(TOP).v target
|
| /dports/misc/py-tvm/incubator-tvm-0.6.1/vta/apps/gemm/hardware/chisel/ |
| H A D | Makefile | 104 verilog: $(chisel_build_dir)/$(TOP).v target
|
| /dports/misc/tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/hardware/chisel/ |
| H A D | Makefile | 107 verilog: $(chisel_build_dir)/$(TOP).v target
|
| /dports/misc/py-tvm/incubator-tvm-0.6.1/vta/apps/tsim_example/hardware/chisel/ |
| H A D | Makefile | 107 verilog: $(chisel_build_dir)/$(TOP).v target
|
| /dports/cad/geda/geda-gaf-1.8.2/gnetlist/scheme/ |
| H A D | gnet-verilog.scm | 653 (define verilog unknown
|
| /dports/misc/tvm/incubator-tvm-0.6.1/vta/hardware/chisel/ |
| H A D | Makefile | 128 verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).v target
|
| /dports/misc/py-tvm/incubator-tvm-0.6.1/vta/hardware/chisel/ |
| H A D | Makefile | 128 verilog: $(chisel_build_dir)/$(TOP).$(CONFIG).v target
|
| /dports/cad/opentimer/OpenTimer-18d28ff/main/utility/ |
| H A D | utility.cpp | 171 std::filesystem::path verilog; in tau15_to_shell() local
|
| /dports/cad/opentimer/OpenTimer-18d28ff/main/tau15/ |
| H A D | tau15.cpp | 18 std::filesystem::path verilog; in main() local
|
| /dports/editors/cudatext/CudaText-1.151.0/app/data/lexlib/ |
| H A D | aliases.ini | 217 verilog=Verilog HDL key
|
| /dports/editors/cudatext/CudaText-1.151.0/app/cudatext.app/Contents/Resources/data/lexlib/ |
| H A D | aliases.ini | 217 verilog=Verilog HDL key
|
| /dports/textproc/kibana7/kibana-7.16.2-darwin-x86_64/node_modules/prismjs/ |
| H A D | components.json | 1378 "verilog": { object
|