1 #ifndef MEMORY_H 2 #define MEMORY_H 3 4 #include "osd_cpu.h" 5 #include <stddef.h> 6 7 8 #define MAX_BANKS 16 9 10 11 /*************************************************************************** 12 Core memory read/write/opbase handler types. 13 ***************************************************************************/ 14 15 /* ----- typedefs for data and offset types ----- */ 16 typedef UINT8 data8_t; 17 typedef UINT16 data16_t; 18 typedef UINT32 data32_t; 19 typedef UINT32 offs_t; 20 typedef UINT32 data_t; 21 22 typedef data_t (*mem_read_handler)(offs_t offset); 23 typedef void (*mem_write_handler)(offs_t offset,data_t data); 24 typedef offs_t (*opbase_handler)(offs_t address); 25 26 #ifdef DJGPP 27 #define READ_HANDLER(name) data_t name(offs_t __attribute__ ((unused)) offset) 28 #define WRITE_HANDLER(name) void name(offs_t __attribute__ ((unused)) offset,data_t __attribute__ ((unused)) data) 29 #define OPBASE_HANDLER(name) offs_t name(offs_t __attribute__ ((unused)) address) 30 #else 31 #define READ_HANDLER(name) data_t name(offs_t offset) 32 #define WRITE_HANDLER(name) void name(offs_t offset,data_t data) 33 #define OPBASE_HANDLER(name) offs_t name(offs_t address) 34 #endif 35 36 37 38 /*************************************************************************** 39 40 Note that the memory hooks are not passed the actual memory address where 41 the operation takes place, but the offset from the beginning of the block 42 they are assigned to. This makes handling of mirror addresses easier, and 43 makes the handlers a bit more "object oriented". If you handler needs to 44 read/write the main memory area, provide a "base" pointer: it will be 45 initialized by the main engine to point to the beginning of the memory block 46 assigned to the handler. You may also provided a pointer to "size": it 47 will be set to the length of the memory area processed by the handler. 48 49 ***************************************************************************/ 50 51 struct MemoryReadAddress 52 { 53 offs_t start, end; 54 mem_read_handler handler; /* see special values below */ 55 }; 56 57 #define MRA_NOP 0 /* don't care, return 0 */ 58 #define MRA_RAM ((mem_read_handler)-1) /* plain RAM location (return its contents) */ 59 #define MRA_ROM ((mem_read_handler)-2) /* plain ROM location (return its contents) */ 60 #define MRA_BANK1 ((mem_read_handler)-10) /* bank memory */ 61 #define MRA_BANK2 ((mem_read_handler)-11) /* bank memory */ 62 #define MRA_BANK3 ((mem_read_handler)-12) /* bank memory */ 63 #define MRA_BANK4 ((mem_read_handler)-13) /* bank memory */ 64 #define MRA_BANK5 ((mem_read_handler)-14) /* bank memory */ 65 #define MRA_BANK6 ((mem_read_handler)-15) /* bank memory */ 66 #define MRA_BANK7 ((mem_read_handler)-16) /* bank memory */ 67 #define MRA_BANK8 ((mem_read_handler)-17) /* bank memory */ 68 #define MRA_BANK9 ((mem_read_handler)-18) /* bank memory */ 69 #define MRA_BANK10 ((mem_read_handler)-19) /* bank memory */ 70 #define MRA_BANK11 ((mem_read_handler)-20) /* bank memory */ 71 #define MRA_BANK12 ((mem_read_handler)-21) /* bank memory */ 72 #define MRA_BANK13 ((mem_read_handler)-22) /* bank memory */ 73 #define MRA_BANK14 ((mem_read_handler)-23) /* bank memory */ 74 #define MRA_BANK15 ((mem_read_handler)-24) /* bank memory */ 75 #define MRA_BANK16 ((mem_read_handler)-25) /* bank memory */ 76 77 struct MemoryWriteAddress 78 { 79 offs_t start, end; 80 mem_write_handler handler; /* see special values below */ 81 unsigned char **base; /* optional (see explanation above) */ 82 size_t *size; /* optional (see explanation above) */ 83 }; 84 85 #define MWA_NOP 0 /* do nothing */ 86 #define MWA_RAM ((mem_write_handler)-1) /* plain RAM location (store the value) */ 87 #define MWA_ROM ((mem_write_handler)-2) /* plain ROM location (do nothing) */ 88 /* 89 If the CPU opcodes are encrypted, they are fetched from a different memory space. 90 In such a case, if the program dynamically creates code in RAM and executes it, 91 it won't work unless you use MWA_RAMROM to affect both memory spaces. 92 */ 93 #define MWA_RAMROM ((mem_write_handler)-3) 94 #define MWA_BANK1 ((mem_write_handler)-10) /* bank memory */ 95 #define MWA_BANK2 ((mem_write_handler)-11) /* bank memory */ 96 #define MWA_BANK3 ((mem_write_handler)-12) /* bank memory */ 97 #define MWA_BANK4 ((mem_write_handler)-13) /* bank memory */ 98 #define MWA_BANK5 ((mem_write_handler)-14) /* bank memory */ 99 #define MWA_BANK6 ((mem_write_handler)-15) /* bank memory */ 100 #define MWA_BANK7 ((mem_write_handler)-16) /* bank memory */ 101 #define MWA_BANK8 ((mem_write_handler)-17) /* bank memory */ 102 #define MWA_BANK9 ((mem_write_handler)-18) /* bank memory */ 103 #define MWA_BANK10 ((mem_write_handler)-19) /* bank memory */ 104 #define MWA_BANK11 ((mem_write_handler)-20) /* bank memory */ 105 #define MWA_BANK12 ((mem_write_handler)-21) /* bank memory */ 106 #define MWA_BANK13 ((mem_write_handler)-22) /* bank memory */ 107 #define MWA_BANK14 ((mem_write_handler)-23) /* bank memory */ 108 #define MWA_BANK15 ((mem_write_handler)-24) /* bank memory */ 109 #define MWA_BANK16 ((mem_write_handler)-25) /* bank memory */ 110 111 112 113 /*************************************************************************** 114 115 IN and OUT ports are handled like memory accesses, the hook template is the 116 same so you can interchange them. Of course there is no 'base' pointer for 117 IO ports. 118 119 ***************************************************************************/ 120 121 struct IOReadPort 122 { 123 int start,end; 124 mem_read_handler handler; /* see special values below */ 125 }; 126 127 #define IORP_NOP 0 /* don't care, return 0 */ 128 129 130 struct IOWritePort 131 { 132 int start,end; 133 mem_write_handler handler; /* see special values below */ 134 }; 135 136 #define IOWP_NOP 0 /* do nothing */ 137 138 139 /*************************************************************************** 140 141 If a memory region contains areas that are outside of the ROM region for 142 an address space, the memory system will allocate an array of structures 143 to track the external areas. 144 145 ***************************************************************************/ 146 147 #define MAX_EXT_MEMORY 64 148 149 struct ExtMemory 150 { 151 int start,end,region; 152 unsigned char *data; 153 }; 154 155 extern struct ExtMemory ext_memory[MAX_EXT_MEMORY]; 156 157 158 159 /*************************************************************************** 160 161 For a given number of address bits, we need to determine how many elements 162 there are in the first and second-order lookup tables. We also need to know 163 how many low-order bits to ignore. The ABITS* values represent these 164 constants for each address space type we support. 165 166 ***************************************************************************/ 167 168 /* memory element block size */ 169 #define MH_SBITS 8 /* sub element bank size */ 170 #define MH_PBITS 8 /* port current element size */ 171 #define MH_ELEMAX 64 /* sub elements limit */ 172 #define MH_HARDMAX 64 /* hardware functions limit */ 173 174 /* 16 bits address */ 175 #define ABITS1_16 12 176 #define ABITS2_16 4 177 #define ABITS_MIN_16 0 /* minimum memory block is 1 byte */ 178 /* 16 bits address (little endian word access) */ 179 #define ABITS1_16LEW 12 180 #define ABITS2_16LEW 3 181 #define ABITS_MIN_16LEW 1 /* minimum memory block is 2 bytes */ 182 /* 16 bits address (big endian word access) */ 183 #define ABITS1_16BEW 12 184 #define ABITS2_16BEW 3 185 #define ABITS_MIN_16BEW 1 /* minimum memory block is 2 bytes */ 186 /* 20 bits address */ 187 #define ABITS1_20 12 188 #define ABITS2_20 8 189 #define ABITS_MIN_20 0 /* minimum memory block is 1 byte */ 190 /* 21 bits address */ 191 #define ABITS1_21 13 192 #define ABITS2_21 8 193 #define ABITS_MIN_21 0 /* minimum memory block is 1 byte */ 194 /* 24 bits address (word access - byte granularity) */ 195 #define ABITS1_24 16 196 #define ABITS2_24 8 197 #define ABITS_MIN_24 0 /* minimum memory block is 1 byte */ 198 /* 24 bits address (big endian - word access) */ 199 #define ABITS1_24BEW 15 200 #define ABITS2_24BEW 8 201 #define ABITS_MIN_24BEW 1 /* minimum memory block is 2 bytes */ 202 /* 26 bits address (little endian - dword access) */ 203 #define ABITS1_26LEW 16 204 #define ABITS2_26LEW 8 205 #define ABITS_MIN_26LEW 2 /* minimum memory block is 4 bytes */ 206 /* 29 bits address (dword access) */ 207 #define ABITS1_29 19 208 #define ABITS2_29 8 209 #define ABITS_MIN_29 2 /* minimum memory block is 4 bytes */ 210 /* 32 bits address (dword access) */ 211 #define ABITS1_32 23 212 #define ABITS2_32 8 213 #define ABITS_MIN_32 1 /* minimum memory block is 2 bytes */ 214 /* 32 bits address (little endian dword access) */ 215 #define ABITS1_32LEW 23 216 #define ABITS2_32LEW 8 217 #define ABITS_MIN_32LEW 1 /* minimum memory block is 2 bytes */ 218 /* mask bits */ 219 #define MHMASK(abits) (0xffffffff >> (32 - abits)) 220 221 222 /*************************************************************************** 223 224 Global variables 225 226 ***************************************************************************/ 227 228 typedef unsigned char MHELE; 229 230 extern MHELE ophw; /* opcode handler */ 231 extern MHELE *cur_mrhard; /* current set of read handlers */ 232 extern MHELE *cur_mwhard; /* current set of write handlers */ 233 234 extern unsigned char *OP_RAM; /* opcode RAM base */ 235 extern unsigned char *OP_ROM; /* opcode ROM base */ 236 extern unsigned char *cpu_bankbase[]; /* array of bank bases */ 237 238 239 240 /*************************************************************************** 241 242 Macros 243 244 ***************************************************************************/ 245 246 /* ----- 16-bit memory accessing ----- */ 247 #define READ_WORD(a) (*(UINT16 *)(a)) 248 #define WRITE_WORD(a,d) (*(UINT16 *)(a) = (d)) 249 #define COMBINE_WORD(w,d) (((w) & ((d) >> 16)) | ((d) & 0xffff)) 250 #define COMBINE_WORD_MEM(a,d) (WRITE_WORD((a), (READ_WORD(a) & ((d) >> 16)) | (d))) 251 252 /* ----- opcode reading ----- */ 253 #define cpu_readop(A) (OP_ROM[A]) 254 #define cpu_readop16(A) READ_WORD(&OP_ROM[A]) 255 #define cpu_readop_arg(A) (OP_RAM[A]) 256 #define cpu_readop_arg16(A) READ_WORD(&OP_RAM[A]) 257 258 /* ----- bank switching for CPU cores ----- */ 259 #define change_pc_generic(pc,abits2,abitsmin,shift,setop) \ 260 { \ 261 if (cur_mrhard[(pc)>>(abits2+abitsmin+shift)] != ophw) \ 262 setop(pc); \ 263 } 264 #define change_pc(pc) change_pc_generic(pc, ABITS2_16, ABITS_MIN_16, 0, cpu_setOPbase16) 265 #define change_pc16(pc) change_pc_generic(pc, ABITS2_16, ABITS_MIN_16, 0, cpu_setOPbase16) 266 #define change_pc16bew(pc) change_pc_generic(pc, ABITS2_16BEW, ABITS_MIN_16BEW, 0, cpu_setOPbase16bew) 267 #define change_pc16lew(pc) change_pc_generic(pc, ABITS2_16LEW, ABITS_MIN_16LEW, 0, cpu_setOPbase16lew) 268 #define change_pc20(pc) change_pc_generic(pc, ABITS2_20, ABITS_MIN_20, 0, cpu_setOPbase20) 269 #define change_pc21(pc) change_pc_generic(pc, ABITS2_21, ABITS_MIN_21, 0, cpu_setOPbase21) 270 #define change_pc24(pc) change_pc_generic(pc, ABITS2_24, ABITS_MIN_24, 0, cpu_setOPbase24) 271 #define change_pc24bew(pc) change_pc_generic(pc, ABITS2_24BEW, ABITS_MIN_24BEW, 0, cpu_setOPbase24bew) 272 #define change_pc26lew(pc) change_pc_generic(pc, ABITS2_26LEW, ABITS_MIN_26LEW, 0, cpu_setOPbase26lew) 273 #define change_pc29(pc) change_pc_generic(pc, ABITS2_29, ABITS_MIN_29, 3, cpu_setOPbase29) 274 #define change_pc32(pc) change_pc_generic(pc, ABITS2_32, ABITS_MIN_32, 0, cpu_setOPbase32) 275 #define change_pc32lew(pc) change_pc_generic(pc, ABITS2_32LEW, ABITS_MIN_32LEW, 0, cpu_setOPbase32lew) 276 277 /* ----- for use OPbaseOverride driver, request override callback to next cpu_setOPbase ----- */ 278 #define catch_nextBranch() (ophw = 0xff) 279 280 /* ----- bank switching macro ----- */ 281 #define cpu_setbank(bank, base) \ 282 { \ 283 if (bank >= 1 && bank <= MAX_BANKS) \ 284 { \ 285 cpu_bankbase[bank] = (UINT8 *)(base); \ 286 if (ophw == bank) \ 287 { \ 288 ophw = 0xff; \ 289 cpu_setOPbase16(cpu_get_pc()); \ 290 } \ 291 } \ 292 } 293 294 295 /*************************************************************************** 296 297 Function prototypes 298 299 ***************************************************************************/ 300 301 /* ----- memory setup function ----- */ 302 int memory_init(void); 303 void memory_shutdown(void); 304 void memorycontextswap(int activecpu); 305 306 /* memory hardware element map */ 307 /* value: */ 308 #define HT_RAM 0 /* RAM direct */ 309 #define HT_BANK1 1 /* bank memory #1 */ 310 #define HT_BANK2 2 /* bank memory #2 */ 311 #define HT_BANK3 3 /* bank memory #3 */ 312 #define HT_BANK4 4 /* bank memory #4 */ 313 #define HT_BANK5 5 /* bank memory #5 */ 314 #define HT_BANK6 6 /* bank memory #6 */ 315 #define HT_BANK7 7 /* bank memory #7 */ 316 #define HT_BANK8 8 /* bank memory #8 */ 317 #define HT_BANK9 9 /* bank memory #9 */ 318 #define HT_BANK10 10 /* bank memory #10 */ 319 #define HT_BANK11 11 /* bank memory #11 */ 320 #define HT_BANK12 12 /* bank memory #12 */ 321 #define HT_BANK13 13 /* bank memory #13 */ 322 #define HT_BANK14 14 /* bank memory #14 */ 323 #define HT_BANK15 15 /* bank memory #15 */ 324 #define HT_BANK16 16 /* bank memory #16 */ 325 #define HT_NON 17 /* non mapped memory */ 326 #define HT_NOP 18 /* NOP memory */ 327 #define HT_RAMROM 19 /* RAM ROM memory */ 328 #define HT_ROM 20 /* ROM memory */ 329 330 #define HT_USER 21 /* user functions */ 331 /* [MH_HARDMAX]-0xff link to sub memory element */ 332 /* (value-MH_HARDMAX)<<MH_SBITS -> element bank */ 333 334 #define HT_BANKMAX (HT_BANK1 + MAX_BANKS - 1) 335 336 #ifdef MSB_FIRST 337 #define BYTE_XOR_BE(a) (a) 338 #define BYTE_XOR_LE(a) ((a) ^ 1) 339 #else 340 #define BYTE_XOR_BE(a) ((a) ^ 1) 341 #define BYTE_XOR_LE(a) (a) 342 #endif 343 344 /* stupid workarounds so that we can generate an address mask that works even for 32 bits */ 345 #define ADDRESS_TOPBIT(abits) (1UL << (ABITS1_##abits + ABITS2_##abits + ABITS_MIN_##abits - 1)) 346 #define ADDRESS_MASK(abits) (ADDRESS_TOPBIT(abits) | (ADDRESS_TOPBIT(abits) - 1)) 347 348 extern unsigned char *cpu_bankbase[HT_BANKMAX + 1]; 349 350 /* ----- memory read functions ----- */ 351 352 extern MHELE *cur_mrhard; 353 extern MHELE readhardware[MH_ELEMAX << MH_SBITS]; /* mem/port read */ 354 extern mem_read_handler memoryreadhandler[MH_HARDMAX]; 355 extern int memoryreadoffset[MH_HARDMAX]; 356 357 #ifdef MAME_MEMINLINE 358 INLINE READ_HANDLER(cpu_readmem16); 359 INLINE READ_HANDLER(cpu_readmem16bew); 360 INLINE READ_HANDLER(cpu_readmem16bew_word); 361 INLINE READ_HANDLER(cpu_readmem16lew); 362 INLINE READ_HANDLER(cpu_readmem16lew_word); 363 INLINE READ_HANDLER(cpu_readmem20); 364 INLINE READ_HANDLER(cpu_readmem21); 365 INLINE READ_HANDLER(cpu_readmem24); 366 INLINE READ_HANDLER(cpu_readmem24bew); 367 INLINE READ_HANDLER(cpu_readmem24bew_word); 368 INLINE READ_HANDLER(cpu_readmem24bew_dword); 369 INLINE READ_HANDLER(cpu_readmem26lew); 370 INLINE READ_HANDLER(cpu_readmem26lew_word); 371 INLINE READ_HANDLER(cpu_readmem26lew_dword); 372 INLINE READ_HANDLER(cpu_readmem29); 373 INLINE READ_HANDLER(cpu_readmem29_word); 374 INLINE READ_HANDLER(cpu_readmem29_dword); 375 INLINE READ_HANDLER(cpu_readmem32); 376 INLINE READ_HANDLER(cpu_readmem32_word); 377 INLINE READ_HANDLER(cpu_readmem32_dword); 378 INLINE READ_HANDLER(cpu_readmem32lew); 379 INLINE READ_HANDLER(cpu_readmem32lew_word); 380 INLINE READ_HANDLER(cpu_readmem32lew_dword); 381 #include "memory_read.h" 382 #else 383 READ_HANDLER(cpu_readmem16); 384 READ_HANDLER(cpu_readmem16bew); 385 READ_HANDLER(cpu_readmem16bew_word); 386 READ_HANDLER(cpu_readmem16lew); 387 READ_HANDLER(cpu_readmem16lew_word); 388 READ_HANDLER(cpu_readmem20); 389 READ_HANDLER(cpu_readmem21); 390 READ_HANDLER(cpu_readmem24); 391 READ_HANDLER(cpu_readmem24bew); 392 READ_HANDLER(cpu_readmem24bew_word); 393 READ_HANDLER(cpu_readmem24bew_dword); 394 READ_HANDLER(cpu_readmem26lew); 395 READ_HANDLER(cpu_readmem26lew_word); 396 READ_HANDLER(cpu_readmem26lew_dword); 397 READ_HANDLER(cpu_readmem29); 398 READ_HANDLER(cpu_readmem29_word); 399 READ_HANDLER(cpu_readmem29_dword); 400 READ_HANDLER(cpu_readmem32); 401 READ_HANDLER(cpu_readmem32_word); 402 READ_HANDLER(cpu_readmem32_dword); 403 READ_HANDLER(cpu_readmem32lew); 404 READ_HANDLER(cpu_readmem32lew_word); 405 READ_HANDLER(cpu_readmem32lew_dword); 406 #endif 407 408 /* ----- memory write functions ----- */ 409 410 extern MHELE *cur_mwhard; 411 extern MHELE writehardware[MH_ELEMAX << MH_SBITS]; /* mem/port write */ 412 extern mem_write_handler memorywritehandler[MH_HARDMAX]; 413 extern int memorywriteoffset[MH_HARDMAX]; 414 415 #ifdef MAME_MEMINLINE 416 INLINE WRITE_HANDLER(cpu_writemem16); 417 INLINE WRITE_HANDLER(cpu_writemem16bew); 418 INLINE WRITE_HANDLER(cpu_writemem16bew_word); 419 INLINE WRITE_HANDLER(cpu_writemem16lew); 420 INLINE WRITE_HANDLER(cpu_writemem16lew_word); 421 INLINE WRITE_HANDLER(cpu_writemem20); 422 INLINE WRITE_HANDLER(cpu_writemem21); 423 INLINE WRITE_HANDLER(cpu_writemem24); 424 INLINE WRITE_HANDLER(cpu_writemem24bew); 425 INLINE WRITE_HANDLER(cpu_writemem24bew_word); 426 INLINE WRITE_HANDLER(cpu_writemem24bew_dword); 427 INLINE WRITE_HANDLER(cpu_writemem26lew); 428 INLINE WRITE_HANDLER(cpu_writemem26lew_word); 429 INLINE WRITE_HANDLER(cpu_writemem26lew_dword); 430 INLINE WRITE_HANDLER(cpu_writemem29); 431 INLINE WRITE_HANDLER(cpu_writemem29_word); 432 INLINE WRITE_HANDLER(cpu_writemem29_dword); 433 INLINE WRITE_HANDLER(cpu_writemem32); 434 INLINE WRITE_HANDLER(cpu_writemem32_word); 435 INLINE WRITE_HANDLER(cpu_writemem32_dword); 436 INLINE WRITE_HANDLER(cpu_writemem32lew); 437 INLINE WRITE_HANDLER(cpu_writemem32lew_word); 438 INLINE WRITE_HANDLER(cpu_writemem32lew_dword); 439 #include "memory_write.h" 440 #else 441 WRITE_HANDLER(cpu_writemem16); 442 WRITE_HANDLER(cpu_writemem16bew); 443 WRITE_HANDLER(cpu_writemem16bew_word); 444 WRITE_HANDLER(cpu_writemem16lew); 445 WRITE_HANDLER(cpu_writemem16lew_word); 446 WRITE_HANDLER(cpu_writemem20); 447 WRITE_HANDLER(cpu_writemem21); 448 WRITE_HANDLER(cpu_writemem24); 449 WRITE_HANDLER(cpu_writemem24bew); 450 WRITE_HANDLER(cpu_writemem24bew_word); 451 WRITE_HANDLER(cpu_writemem24bew_dword); 452 WRITE_HANDLER(cpu_writemem26lew); 453 WRITE_HANDLER(cpu_writemem26lew_word); 454 WRITE_HANDLER(cpu_writemem26lew_dword); 455 WRITE_HANDLER(cpu_writemem29); 456 WRITE_HANDLER(cpu_writemem29_word); 457 WRITE_HANDLER(cpu_writemem29_dword); 458 WRITE_HANDLER(cpu_writemem32); 459 WRITE_HANDLER(cpu_writemem32_word); 460 WRITE_HANDLER(cpu_writemem32_dword); 461 WRITE_HANDLER(cpu_writemem32lew); 462 WRITE_HANDLER(cpu_writemem32lew_word); 463 WRITE_HANDLER(cpu_writemem32lew_dword); 464 #endif 465 466 /* ----- port I/O functions ----- */ 467 int cpu_readport(int port); 468 void cpu_writeport(int port, int value); 469 470 /* ----- dynamic memory/port mapping ----- */ 471 void *install_mem_read_handler(int cpu, int start, int end, mem_read_handler handler); 472 void *install_mem_write_handler(int cpu, int start, int end, mem_write_handler handler); 473 void *install_port_read_handler(int cpu, int start, int end, mem_read_handler handler); 474 void *install_port_write_handler(int cpu, int start, int end, mem_write_handler handler); 475 476 /* ----- dynamic bank handlers ----- */ 477 void cpu_setbankhandler_r(int bank, mem_read_handler handler); 478 void cpu_setbankhandler_w(int bank, mem_write_handler handler); 479 480 /* ----- opcode base control ---- */ 481 void cpu_setOPbase16(int pc); 482 void cpu_setOPbase16bew(int pc); 483 void cpu_setOPbase16lew(int pc); 484 void cpu_setOPbase20(int pc); 485 void cpu_setOPbase21(int pc); 486 void cpu_setOPbase24(int pc); 487 void cpu_setOPbase24bew(int pc); 488 void cpu_setOPbase26lew(int pc); 489 void cpu_setOPbase29(int pc); 490 void cpu_setOPbase32(int pc); 491 void cpu_setOPbase32lew(int pc); 492 void cpu_setOPbaseoverride(int cpu, opbase_handler function); 493 494 /* ----- harder-to-explain functions ---- */ 495 496 /* use this to set the a different opcode base address when using a CPU with 497 opcodes and data encrypted separately */ 498 void memory_set_opcode_base(int cpu, unsigned char *base); 499 500 /* look up a chunk of memory and get its start/end addresses, and its base. 501 Pass in the cpu number and the offset. It will find the chunk containing 502 that offset and return the start and end addresses, along with a pointer to 503 the base of the memory. 504 This can be used (carefully!) by drivers that wish to access memory directly 505 without going through the readmem/writemem accessors (e.g., blitters). */ 506 unsigned char *findmemorychunk(int cpu, int offset, int *chunkstart, int *chunkend); 507 508 #endif 509 510