1library IEEE; 2use IEEE.STD_LOGIC_1164.ALL; 3library STD; 4use IEEE.NUMERIC_STD.ALL; 5 6entity DSPn is 7 port( 8 CLK : in std_logic; 9 CE : in std_logic; 10 RST_N : in std_logic; 11 ENABLE : in std_logic; 12 A0 : in std_logic; 13 DI : in std_logic_vector(7 downto 0); 14 DO : out std_logic_vector(7 downto 0); 15 CS_N : in std_logic; 16 RD_N : in std_logic; 17 WR_N : in std_logic; 18 19 DP_ADDR : in std_logic_vector(11 downto 0); 20 DP_SEL : in std_logic; 21 22 VER : in std_logic_vector(2 downto 0);--00-DSP1B, 01-DSP2, 10-DSP3, 11-DSP4 23 24 BRK_OUT : out std_logic; 25 DBG_REG : in std_logic_vector(7 downto 0); 26 DBG_DAT_IN : in std_logic_vector(7 downto 0); 27 DBG_DAT_OUT : out std_logic_vector(7 downto 0); 28 DBG_DAT_WR : in std_logic 29 ); 30end DSPn; 31 32architecture rtl of DSPn is 33 34 constant ACC_A : integer range 0 to 1 := 0; 35 constant ACC_B : integer range 0 to 1 := 1; 36 constant FLAG_OV0 : integer range 0 to 5 := 0; 37 constant FLAG_OV1 : integer range 0 to 5 := 1; 38 constant FLAG_Z : integer range 0 to 5 := 2; 39 constant FLAG_C : integer range 0 to 5 := 3; 40 constant FLAG_S0 : integer range 0 to 5 := 4; 41 constant FLAG_S1 : integer range 0 to 5 := 5; 42 43 constant INSTR_OP: std_logic_vector(1 downto 0) := "00"; 44 constant INSTR_RT: std_logic_vector(1 downto 0) := "01"; 45 constant INSTR_JP: std_logic_vector(1 downto 0) := "10"; 46 constant INSTR_LD: std_logic_vector(1 downto 0) := "11"; 47 48 -- IO Registers 49 signal DR : std_logic_vector(15 downto 0); 50 signal SR : std_logic_vector(15 downto 0); 51 signal DP : std_logic_vector(10 downto 0); 52 signal RP : std_logic_vector(10 downto 0); 53 signal PC : std_logic_vector(10 downto 0); 54 type StackRam_t is array (0 to 7) of std_logic_vector(10 downto 0); 55 signal STACK_RAM : StackRam_t; 56 signal SP : unsigned(2 downto 0); 57 signal K, L, M, N : std_logic_vector(15 downto 0); 58 signal P, Q : std_logic_vector(15 downto 0); 59 type Acc_t is array (0 to 1) of std_logic_vector(15 downto 0); 60 signal ACC : Acc_t; 61 type Flags_t is array (0 to 1) of std_logic_vector(5 downto 0); 62 signal FLAGS : Flags_t; 63 signal TR, TRB : std_logic_vector(15 downto 0); 64 signal SI, SO : std_logic_vector(15 downto 0); 65 signal SGN : std_logic_vector(15 downto 0); 66 signal RQM : std_logic; 67 signal DRS, DRC : std_logic; 68 signal USF0, USF1 : std_logic; 69 signal P0, P1 : std_logic; 70 signal EI, DMA : std_logic; 71 72 signal OP_DST : std_logic_vector(3 downto 0); 73 signal OP_SRC : std_logic_vector(3 downto 0); 74 signal OP_RP : std_logic; 75 signal OP_DPH : std_logic_vector(3 downto 0); 76 signal OP_DPL : std_logic_vector(1 downto 0); 77 signal OP_A : unsigned(0 downto 0); 78 signal OP_ALU : std_logic_vector(3 downto 0); 79 signal OP_P : std_logic_vector(1 downto 0); 80 signal OP_ID : std_logic_vector(15 downto 0); 81 signal OP_NA : std_logic_vector(10 downto 0); 82 signal OP_BRCH : std_logic_vector(8 downto 0); 83 signal OP_INSTR : std_logic_vector(1 downto 0); 84 85 signal IDB : std_logic_vector(15 downto 0); 86 signal ALU_R : std_logic_vector(15 downto 0); 87 88 signal PROG_ROM_ADDR : std_logic_vector(12 downto 0); 89 signal PROG_ROM_Q : std_logic_vector(23 downto 0); 90 signal DATA_ROM_ADDR : std_logic_vector(12 downto 0); 91 signal DATA_ROM_Q : std_logic_vector(15 downto 0); 92 signal DATA_RAM_ADDR_A, DATA_RAM_ADDR_B : std_logic_vector(10 downto 0); 93 signal DATA_RAM_Q_A, DATA_RAM_Q_B : std_logic_vector(15 downto 0); 94 signal DATA_RAM_WE : std_logic; 95 96 signal EN : std_logic; 97 signal RD_Nr, WR_Nr : std_logic_vector(2 downto 0); 98 signal PORT_ACTIVE : std_logic; 99 100 --debug 101 signal DBG_RUN_LAST : std_logic; 102 signal DBG_DAT_WRr : std_logic; 103 signal DBG_BRK_ADDR : std_logic_vector(10 downto 0) := (others => '1'); 104 signal DBG_CTRL : std_logic_vector(7 downto 0) := (others => '0'); 105 106 component dp16k_wrapper_8bit 107 generic ( 108 addr_width : natural := 11 109 ); 110 port ( 111 clock : in STD_LOGIC; 112 113 address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0); 114 data_a : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0'); 115 enable_a : in STD_LOGIC := '1'; 116 wren_a : in STD_LOGIC := '0'; 117 q_a : out STD_LOGIC_VECTOR (7 DOWNTO 0); 118 cs_a : in std_logic := '1'; 119 120 address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0'); 121 data_b : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0'); 122 enable_b : in STD_LOGIC := '1'; 123 wren_b : in STD_LOGIC := '0'; 124 q_b : out STD_LOGIC_VECTOR (7 DOWNTO 0); 125 cs_b : in std_logic := '1' 126 ); 127 end component; 128 component sprom_verilog is 129 generic ( 130 addr_width : integer := 8; 131 data_width : integer := 8; 132 length : integer := 8; 133 hex_file : string := "" 134 ); 135 port 136 ( 137 clock : in STD_LOGIC; 138 address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0); 139 q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) 140 ); 141 end component; 142 143begin 144 145 EN <= ENABLE and CE; 146 147 OP_INSTR <= PROG_ROM_Q(23 downto 22); 148 OP_P <= PROG_ROM_Q(21 downto 20); 149 OP_ALU <= PROG_ROM_Q(19 downto 16); 150 OP_A <= unsigned(PROG_ROM_Q(15 downto 15)); 151 OP_DPL <= PROG_ROM_Q(14 downto 13); 152 OP_DPH <= PROG_ROM_Q(12 downto 9); 153 OP_RP <= PROG_ROM_Q(8); 154 OP_SRC <= PROG_ROM_Q(7 downto 4); 155 OP_DST <= PROG_ROM_Q(3 downto 0); 156 OP_ID <= PROG_ROM_Q(21 downto 6) when OP_INSTR = INSTR_LD else IDB; 157 OP_NA <= PROG_ROM_Q(12 downto 2); 158 OP_BRCH <= PROG_ROM_Q(21 downto 13); 159 160 161 SGN <= x"8000" xor (0 to 15 => FLAGS(ACC_A)(FLAG_S1)); 162 SR <= RQM & USF1 & USF0 & DRS & DMA & DRC & "00" & EI & "00000" & P1 & P0; 163 SI <= (others => '0'); 164 IDB <= TRB when OP_SRC = x"0" else 165 ACC(ACC_A) when OP_SRC = x"1" else 166 ACC(ACC_B) when OP_SRC = x"2" else 167 TR when OP_SRC = x"3" else 168 "00000" & DP when OP_SRC = x"4" and VER(2) = '1' else 169 "00000" & RP when OP_SRC = x"5" and VER(2) = '1' else 170 x"00" & DP(7 downto 0) when OP_SRC = x"4" else 171 "000000" & RP(9 downto 0) when OP_SRC = x"5" else 172 DATA_ROM_Q when OP_SRC = x"6" else 173 SGN when OP_SRC = x"7" else 174 DR when OP_SRC = x"8" else 175 DR when OP_SRC = x"9" else 176 SR when OP_SRC = x"A" else 177 SI when OP_SRC = x"B" else 178 SI when OP_SRC = x"C" else 179 K when OP_SRC = x"D" else 180 L when OP_SRC = x"E" else 181 DATA_RAM_Q_A when OP_SRC = x"F" else 182 x"0000"; 183 184 --ALU 185 Q <= ACC(to_integer(OP_A)); 186 P <= x"0001" when OP_ALU(3 downto 1) = "100" else 187 DATA_RAM_Q_A when OP_P = "00" else 188 IDB when OP_P = "01" else 189 M when OP_P = "10" else 190 N; 191 192 process( OP_ALU, P, Q, ALU_R, FLAGS, OP_A) 193 variable FC : std_logic; 194 variable CARRY : unsigned(15 downto 0); 195 begin 196 FC := FLAGS(to_integer(not OP_A))(FLAG_C); 197 CARRY := (0 => FC, others => '0'); 198 case OP_ALU is 199 when x"1" => 200 ALU_R <= Q or P; 201 when x"2" => 202 ALU_R <= Q and P; 203 when x"3" => 204 ALU_R <= Q xor P; 205 when x"4" => 206 ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P)); 207 when x"5" => 208 ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P)); 209 when x"6" => 210 ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P) - CARRY); 211 when x"7" => 212 ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P) + CARRY); 213 when x"8" => 214 ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P)); 215 when x"9" => 216 ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P)); 217 when x"A" => 218 ALU_R <= not Q; 219 when x"B" => 220 ALU_R <= Q(15) & Q(15 downto 1); 221 when x"C" => 222 ALU_R <= Q(14 downto 0) & FC; 223 when x"D" => 224 ALU_R <= Q(13 downto 0) & "11"; 225 when x"E" => 226 ALU_R <= Q(11 downto 0) & "1111"; 227 when x"F" => 228 ALU_R <= Q(7 downto 0) & Q(15 downto 8); 229 when others => 230 ALU_R <= Q; 231 end case; 232 end process; 233 234 --Flags 235 process(CLK, RST_N) 236 variable OV0 : std_logic; 237 begin 238 if RST_N = '0' then 239 FLAGS <= (others => (others => '0')); 240 elsif rising_edge(CLK) then 241 if EN = '1' then 242 if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_ALU /= x"0" then 243 FLAGS(to_integer(OP_A))(FLAG_S0) <= ALU_R(15); 244 245 if ALU_R = x"0000" then 246 FLAGS(to_integer(OP_A))(FLAG_Z) <= '1'; 247 else 248 FLAGS(to_integer(OP_A))(FLAG_Z) <= '0'; 249 end if; 250 251 case OP_ALU is 252 when x"1" | x"2" | x"3" | x"A" | x"D" | x"E" | x"F" => 253 FLAGS(to_integer(OP_A))(FLAG_C) <= '0'; 254 when x"4" | x"6" | x"8" => 255 if ALU_R > Q then 256 FLAGS(to_integer(OP_A))(FLAG_C) <= '1'; 257 else 258 FLAGS(to_integer(OP_A))(FLAG_C) <= '0'; 259 end if; 260 when x"5" | x"7" | x"9" => 261 if ALU_R < Q then 262 FLAGS(to_integer(OP_A))(FLAG_C) <= '1'; 263 else 264 FLAGS(to_integer(OP_A))(FLAG_C) <= '0'; 265 end if; 266 when x"B" => 267 FLAGS(to_integer(OP_A))(FLAG_C) <= Q(0); 268 when x"C" => 269 FLAGS(to_integer(OP_A))(FLAG_C) <= Q(15); 270 when others => null; 271 end case; 272 273 OV0 := (Q(15) xor ALU_R(15)) and ((Q(15) xor P(15)) xor OP_ALU(0)); 274 case OP_ALU is 275 when x"1" | x"2" | x"3" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => 276 FLAGS(to_integer(OP_A))(FLAG_OV0) <= '0'; 277 FLAGS(to_integer(OP_A))(FLAG_OV1) <= '0'; 278 when x"4" | x"5" | x"6" | x"7" | x"8" | x"9" => 279 FLAGS(to_integer(OP_A))(FLAG_OV0) <= OV0; 280 if OV0 = '1' then 281 FLAGS(to_integer(OP_A))(FLAG_S1) <= FLAGS(to_integer(OP_A))(FLAG_OV1) xor (not ALU_R(15)); 282 FLAGS(to_integer(OP_A))(FLAG_OV1) <= not FLAGS(to_integer(OP_A))(FLAG_OV1); 283 end if; 284 when others => null; 285 end case; 286 end if; 287 end if; 288 end if; 289 end process; 290 291 --Multiplier 292 process(K, L) 293 variable TEMP : signed(30 downto 0); 294 begin 295 TEMP := resize((signed(K) * signed(L)),TEMP'length); 296 M <= std_logic_vector(TEMP(30 downto 15)); 297 N <= std_logic_vector(TEMP(14 downto 0)) & "0"; 298 end process; 299 300 --Registers 301 process(CLK, RST_N) 302 variable DAT : std_logic_vector(15 downto 0); 303 begin 304 if RST_N = '0' then 305 ACC <= (others => (others => '0')); 306 TR <= (others => '0'); 307 DP <= (others => '0'); 308 RP <= (others => '1'); 309 DRC <= '0'; 310 USF1 <= '0'; 311 USF0 <= '0'; 312 DMA <= '0'; 313 EI <= '0'; 314 P1 <= '0'; 315 P0 <= '0'; 316 TRB <= (others => '0'); 317 SO <= (others => '0'); 318 K <= (others => '0'); 319 L <= (others => '0'); 320 elsif rising_edge(CLK) then 321 if EN = '1' then 322 if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) then 323 if OP_ALU /= x"0" then 324 ACC(to_integer(OP_A)) <= ALU_R; 325 end if; 326 327 case OP_DPL is 328 when "01" => 329 DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) + 1); 330 when "10" => 331 DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) - 1); 332 when "11" => 333 DP(3 downto 0) <= (others => '0'); 334 when others => null; 335 end case; 336 DP(7 downto 4) <= DP(7 downto 4) xor OP_DPH; 337 338 if OP_RP = '1' then 339 RP <= std_logic_vector(unsigned(RP) - 1); 340 end if; 341 end if; 342 343 if OP_INSTR /= INSTR_JP then 344 case OP_DST is 345 when x"1" => 346 ACC(ACC_A) <= OP_ID; 347 when x"2" => 348 ACC(ACC_B) <= OP_ID; 349 when x"3" => 350 TR <= OP_ID; 351 when x"4" => 352 DP <= OP_ID(10 downto 0); 353 when x"5" => 354 RP <= OP_ID(10 downto 0); 355 when x"7" => 356 USF1 <= OP_ID(14); 357 USF0 <= OP_ID(13); 358 DMA <= OP_ID(11); 359 DRC <= OP_ID(10); 360 EI <= OP_ID(7); 361 P1 <= OP_ID(1); 362 P0 <= OP_ID(0); 363 when x"8" => 364 SO <= OP_ID; 365 when x"9" => 366 SO <= OP_ID; 367 when x"A" => 368 K <= OP_ID; 369 when x"B" => 370 K <= OP_ID; 371 L <= DATA_ROM_Q; 372 when x"C" => 373 K <= DATA_RAM_Q_B; 374 L <= OP_ID; 375 when x"D" => 376 L <= OP_ID; 377 when x"E" => 378 TRB <= OP_ID; 379 when others => null; 380 end case; 381 end if; 382 end if; 383 end if; 384 end process; 385 386 process(CLK, RST_N) 387 variable NEXT_SP : unsigned(2 downto 0); 388 variable NEXT_PC : std_logic_vector(10 downto 0); 389 variable COND : std_logic; 390 begin 391 if RST_N = '0' then 392 STACK_RAM <= (others => (others => '0')); 393 SP <= (others => '0'); 394 PC <= (others => '0'); 395 elsif rising_edge(CLK) then 396 if EN = '1' then 397 NEXT_PC := std_logic_vector(unsigned(PC) + 1); 398 if OP_INSTR = INSTR_RT then 399 NEXT_SP := SP - 1; 400 PC <= STACK_RAM(to_integer((NEXT_SP(2) and VER(2))&NEXT_SP(1 downto 0))); 401 SP <= NEXT_SP; 402 elsif OP_INSTR = INSTR_JP then 403 case OP_BRCH(5 downto 2) is 404 when "0000" => 405 COND := FLAGS(ACC_A)(FLAG_C) xor (not OP_BRCH(1)); 406 when "0001" => 407 COND := FLAGS(ACC_B)(FLAG_C) xor (not OP_BRCH(1)); 408 when "0010" => 409 COND := FLAGS(ACC_A)(FLAG_Z) xor (not OP_BRCH(1)); 410 when "0011" => 411 COND := FLAGS(ACC_B)(FLAG_Z) xor (not OP_BRCH(1)); 412 when "0100" => 413 COND := FLAGS(ACC_A)(FLAG_OV0) xor (not OP_BRCH(1)); 414 when "0101" => 415 COND := FLAGS(ACC_B)(FLAG_OV0) xor (not OP_BRCH(1)); 416 when "0110" => 417 COND := FLAGS(ACC_A)(FLAG_OV1) xor (not OP_BRCH(1)); 418 when "0111" => 419 COND := FLAGS(ACC_B)(FLAG_OV1) xor (not OP_BRCH(1)); 420 when "1000" => 421 COND := FLAGS(ACC_A)(FLAG_S0) xor (not OP_BRCH(1)); 422 when "1001" => 423 COND := FLAGS(ACC_B)(FLAG_S0) xor (not OP_BRCH(1)); 424 when "1010" => 425 COND := FLAGS(ACC_A)(FLAG_S1) xor (not OP_BRCH(1)); 426 when "1011" => 427 COND := FLAGS(ACC_B)(FLAG_S1) xor (not OP_BRCH(1)); 428 when "1100" => 429 if (DP(3 downto 0) = (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '0') or 430 (DP(3 downto 0) /= (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '1') then 431 COND := '1'; 432 else 433 COND := '0'; 434 end if; 435 when "1111" => 436 COND := RQM xor (not OP_BRCH(1)); 437 when others => 438 COND := '0'; 439 end case; 440 441 if OP_BRCH = "000000000" then 442 PC <= SO(10 downto 0); 443 elsif OP_BRCH(8 downto 6) = "010" and COND = '1' then 444 PC <= OP_NA; 445 elsif OP_BRCH(8 downto 7) = "10" and OP_BRCH(5 downto 0) = "000000" then 446 PC <= OP_NA; 447 if OP_BRCH(6) = '1' then 448 STACK_RAM(to_integer((SP(2) and VER(2))&SP(1 downto 0))) <= NEXT_PC; 449 SP <= SP + 1; 450 end if; 451 else 452 PC <= NEXT_PC; 453 end if; 454 else 455 PC <= NEXT_PC; 456 end if; 457 end if; 458 end if; 459 end process; 460 461 PROG_ROM_ADDR <= std_logic_vector(unsigned(PC) + ("0"&x"000")) when VER="000" else 462 std_logic_vector(unsigned(PC) + ("0"&x"500")) when VER="001" else 463 std_logic_vector(unsigned(PC) + ("0"&x"C00")) when VER="010" else 464 std_logic_vector(unsigned(PC) + ("1"&x"254")) when VER="011" else 465 std_logic_vector(unsigned(PC) + ("1"&x"954")); 466 467 PROG_ROM : sprom_verilog generic map(13, 24, 7018, "../src/chip/DSP/dsp1b23410_p.hex") 468 port map( 469 clock => CLK, 470 address => PROG_ROM_ADDR, 471 q => PROG_ROM_Q 472 ); 473 474 DATA_ROM_ADDR <= VER(2 downto 1) & (VER(0) or (RP(10) and VER(2))) & RP(9 downto 0); 475 DATA_ROM : sprom_verilog generic map(13, 16, 6144, "../src/chip/DSP/dsp1b23410_d.hex") 476 port map( 477 clock => CLK, 478 address => DATA_ROM_ADDR, 479 q => DATA_ROM_Q 480 ); 481 482 DATA_RAM_ADDR_A <= "000" & DP(7 downto 0) when VER(2)='0' else DP; 483 DATA_RAM_ADDR_B <= DP_ADDR(11 downto 1) when DP_SEL = '1' and (WR_N = '0' or RD_N = '0') else DATA_RAM_ADDR_A or x"40"; 484 DATA_RAM_WE <= '1' when OP_INSTR /= INSTR_JP and OP_DST = x"F" and EN = '1' else '0'; 485 486 DATA_RAML : dp16k_wrapper_8bit generic map(11) 487 port map( 488 clock => CLK, 489 address_a => DATA_RAM_ADDR_A, 490 data_a => OP_ID(7 downto 0), 491 wren_a => DATA_RAM_WE, 492 q_a => DATA_RAM_Q_A(7 downto 0), 493 address_b => DATA_RAM_ADDR_B, 494 data_b => DI, 495 wren_b => not WR_N and DP_SEL and not DP_ADDR(0), 496 q_b => DATA_RAM_Q_B(7 downto 0) 497 ); 498 499 DATA_RAMH : dp16k_wrapper_8bit generic map(11) 500 port map( 501 clock => CLK, 502 address_a => DATA_RAM_ADDR_A, 503 data_a => OP_ID(15 downto 8), 504 wren_a => DATA_RAM_WE, 505 q_a => DATA_RAM_Q_A(15 downto 8), 506 address_b => DATA_RAM_ADDR_B, 507 data_b => DI, 508 wren_b => not WR_N and DP_SEL and DP_ADDR(0), 509 q_b => DATA_RAM_Q_B(15 downto 8) 510 ); 511 512 --I/O Ports 513 process(CLK, RST_N) 514 begin 515 if RST_N = '0' then 516 DRS <= '0'; 517 RQM <= '0'; 518 DR <= (others => '0'); 519 WR_Nr <= (others => '1'); 520 RD_Nr <= (others => '1'); 521 PORT_ACTIVE <= '0'; 522 elsif rising_edge(CLK) then 523 if ENABLE = '1' then 524 WR_Nr <= WR_Nr(1 downto 0) & WR_N; 525 RD_Nr <= RD_Nr(1 downto 0) & RD_N; 526 527 if WR_Nr = "110" and CS_N = '0' and A0 = '0' then 528 if DRC = '0' then 529 if DRS = '0' then 530 DR(7 downto 0) <= DI; 531 else 532 DR(15 downto 8) <= DI; 533 end if; 534 else 535 DR(7 downto 0) <= DI; 536 end if; 537 PORT_ACTIVE <= '1'; 538 elsif RD_Nr = "110" and CS_N = '0' and A0 = '0' then 539 PORT_ACTIVE <= '1'; 540 end if; 541 542 if (WR_Nr = "001" or RD_Nr = "001") and PORT_ACTIVE = '1' then 543 if DRC = '0' then 544 if DRS = '0' then 545 DRS <= '1'; 546 else 547 RQM <= '0'; 548 DRS <= '0'; 549 end if; 550 else 551 RQM <= '0'; 552 end if; 553 PORT_ACTIVE <= '0'; 554 elsif EN = '1' then 555 if OP_INSTR /= INSTR_JP and OP_DST = x"6" then 556 DR <= OP_ID; 557 RQM <= '1'; 558 elsif (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_SRC = x"8" then 559 RQM <= '1'; 560 end if; 561 end if; 562 end if; 563 end if; 564 end process; 565 566 process( A0, SR, DR, DRC, DRS, DP_SEL, DP_ADDR, DATA_RAM_Q_B ) 567 begin 568 if DP_SEL = '1' then 569 if DP_ADDR(0) = '0' then 570 DO <= DATA_RAM_Q_B(7 downto 0); 571 else 572 DO <= DATA_RAM_Q_B(15 downto 8); 573 end if; 574 elsif A0 = '1' then 575 DO <= SR(15 downto 8); 576 else 577 if DRC = '0' then 578 if DRS = '0' then 579 DO <= DR(7 downto 0); 580 else 581 DO <= DR(15 downto 8); 582 end if; 583 else 584 DO <= DR(7 downto 0); 585 end if; 586 end if; 587 end process; 588 589 590 --Debug 591 process(CLK, RST_N) 592 begin 593 if RST_N = '0' then 594 BRK_OUT <= '0'; 595 DBG_RUN_LAST <= '0'; 596 elsif rising_edge(CLK) then 597 if EN = '1' then 598 BRK_OUT <= '0'; 599 if DBG_CTRL(0) = '1' then --step 600 BRK_OUT <= '1'; 601 elsif DBG_CTRL(2) = '1' and DBG_BRK_ADDR = PC then --opcode address break 602 BRK_OUT <= '1'; 603 end if; 604 end if; 605 606 DBG_RUN_LAST <= DBG_CTRL(7); 607 if DBG_CTRL(7) = '1' and DBG_RUN_LAST = '0' then 608 BRK_OUT <= '0'; 609 end if; 610 end if; 611 end process; 612 613 process( RST_N, CLK, DBG_REG, ACC, FLAGS, PC, RP, DP, TR, TRB, K, L, M, N, DR, SR, SP, IDB ) 614 begin 615 case DBG_REG is 616 when x"00" => DBG_DAT_OUT <= ACC(ACC_A)(7 downto 0); 617 when x"01" => DBG_DAT_OUT <= ACC(ACC_A)(15 downto 8); 618 when x"02" => DBG_DAT_OUT <= ACC(ACC_B)(7 downto 0); 619 when x"03" => DBG_DAT_OUT <= ACC(ACC_B)(15 downto 8); 620 when x"04" => DBG_DAT_OUT <= "00"&FLAGS(ACC_A); 621 when x"05" => DBG_DAT_OUT <= "00"&FLAGS(ACC_B); 622 when x"06" => DBG_DAT_OUT <= PC(7 downto 0); 623 when x"07" => DBG_DAT_OUT <= "00000"&PC(10 downto 8); 624 when x"08" => DBG_DAT_OUT <= RP(7 downto 0); 625 when x"09" => DBG_DAT_OUT <= "000000"&RP(9 downto 8); 626 when x"0A" => DBG_DAT_OUT <= DP(7 downto 0); 627 when x"0B" => DBG_DAT_OUT <= TR(7 downto 0); 628 when x"0C" => DBG_DAT_OUT <= TR(15 downto 8); 629 when x"0D" => DBG_DAT_OUT <= TRB(7 downto 0); 630 when x"0E" => DBG_DAT_OUT <= TRB(15 downto 8); 631 when x"0F" => DBG_DAT_OUT <= K(7 downto 0); 632 when x"10" => DBG_DAT_OUT <= K(15 downto 8); 633 when x"11" => DBG_DAT_OUT <= L(7 downto 0); 634 when x"12" => DBG_DAT_OUT <= L(15 downto 8); 635 when x"13" => DBG_DAT_OUT <= M(7 downto 0); 636 when x"14" => DBG_DAT_OUT <= M(15 downto 8); 637 when x"15" => DBG_DAT_OUT <= N(7 downto 0); 638 when x"16" => DBG_DAT_OUT <= N(15 downto 8); 639 when x"17" => DBG_DAT_OUT <= DR(7 downto 0); 640 when x"18" => DBG_DAT_OUT <= DR(15 downto 8); 641 when x"19" => DBG_DAT_OUT <= SR(7 downto 0); 642 when x"1A" => DBG_DAT_OUT <= SR(15 downto 8); 643 when x"1B" => DBG_DAT_OUT <= "00000" & std_logic_vector(SP); 644 when x"1C" => DBG_DAT_OUT <= IDB(7 downto 0); 645 when x"1D" => DBG_DAT_OUT <= IDB(15 downto 8); 646 when others => DBG_DAT_OUT <= x"00"; 647 end case; 648 649 if RST_N = '0' then 650 DBG_DAT_WRr <= '0'; 651 elsif rising_edge(CLK) then 652 DBG_DAT_WRr <= DBG_DAT_WR; 653 if DBG_DAT_WR = '1' and DBG_DAT_WRr = '0' then 654 case DBG_REG is 655 when x"80" => DBG_BRK_ADDR(7 downto 0) <= DBG_DAT_IN; 656 when x"81" => DBG_BRK_ADDR(10 downto 8) <= DBG_DAT_IN(2 downto 0); 657 when x"82" => null; 658 when x"83" => DBG_CTRL <= DBG_DAT_IN; 659 when others => null; 660 end case; 661 end if; 662 end if; 663 end process; 664 665end rtl; 666