1 /***************************************************************************/ 2 /* */ 3 /* HARDware PCEngine */ 4 /* */ 5 /* This header deals with definition of structure and functions used to */ 6 /* handle the pc engine hardware in itself (RAM, IO ports, ...) which were */ 7 /* previously found in pce.h */ 8 /* */ 9 /***************************************************************************/ 10 #ifndef _INCLUDE_HARD_PCE_H 11 #define _INCLUDE_HARD_PCE_H 12 13 #include <stdio.h> 14 15 #include "config.h" 16 #include "cleantyp.h" 17 18 #if defined(SHARED_MEMORY) 19 20 #if !defined(WIN32) 21 22 #include <sys/types.h> 23 #include <sys/ipc.h> 24 #include <sys/shm.h> 25 26 #else 27 28 #include "utils.h" 29 30 #endif 31 32 #endif 33 34 #define PSG_VOICE_REG 0 /* voice index */ 35 36 #define PSG_VOLUME_REG 1 /* master volume */ 37 38 #define PSG_FREQ_LSB_REG 2 /* lower 8 bits of 12 bit frequency */ 39 40 #define PSG_FREQ_MSB_REG 3 /* actually most significant nibble */ 41 42 #define PSG_DDA_REG 4 43 #define PSG_DDA_ENABLE 0x80 /* bit 7 */ 44 #define PSG_DDA_DIRECT_ACCESS 0x40 /* bit 6 */ 45 #define PSG_DDA_VOICE_VOLUME 0x1F /* bits 0-4 */ 46 47 #define PSG_BALANCE_REG 5 48 #define PSG_BALANCE_LEFT 0xF0 /* bits 4-7 */ 49 #define PSG_BALANCE_RIGHT 0x0F /* bits 0-3 */ 50 51 #define PSG_DATA_INDEX_REG 6 52 53 #define PSG_NOISE_REG 7 54 #define PSG_NOISE_ENABLE 0x80 /* bit 7 */ 55 56 /** 57 * Exported functions to access hardware 58 **/ 59 60 void hard_init (void); 61 void hard_term (void); 62 63 void IO_write (UInt16 A,UChar V); 64 UChar IO_read (UInt16 A); 65 void bank_set (UChar P, UChar V); 66 67 extern void (*write_memory_function)(UInt16,UChar); 68 extern UChar (*read_memory_function)(UInt16); 69 70 #define Wr6502(A,V) ((*write_memory_function)((A),(V))) 71 72 #define Rd6502(A) ((*read_memory_function)(A)) 73 74 void dump_pce_cpu_environment(); 75 76 /** 77 * Global structure for all hardware variables 78 **/ 79 80 #include "shared_memory.h" 81 82 /** 83 * Exported variables 84 **/ 85 86 extern struct_hard_pce* hard_pce; 87 // The global structure for all hardware variables 88 89 #define io (*p_io) 90 91 extern IO *p_io; 92 // the global I/O status 93 94 extern UChar *RAM; 95 // mem where variables are stocked (well, RAM... ) 96 // in reality, only 0x2000 bytes are used in a coregraphx and 0x8000 only 97 // in a supergraphx 98 99 extern UChar *WRAM; 100 // extra backup memory 101 // This memory lies in Interface Unit or eventually in RGB adaptator 102 103 extern UChar *VRAM; 104 // Video mem 105 // 0x10000 bytes on coregraphx, the double on supergraphx I think 106 // contain information about the sprites position/status, information 107 // about the pattern and palette to use for each tile, and patterns 108 // for use in sprite/tile rendering 109 110 extern UInt16 *SPRAM; 111 // SPRAM = sprite RAM 112 // The pc engine got a function to transfert a piece VRAM toward the inner 113 // gfx cpu sprite memory from where data will be grabbed to render sprites 114 115 extern UChar *Pal; 116 // PCE->PC Palette convetion array 117 // Each of the 512 available PCE colors (333 RGB -> 512 colors) 118 // got a correspondancy in the 256 fixed colors palette 119 120 extern UChar *VRAM2,*VRAMS; 121 // These are array to keep in memory the result of the linearisation of 122 // PCE sprites and tiles 123 124 extern UChar *vchange,*vchanges; 125 // These array are boolean array to know if we must update the 126 // corresponding linear sprite representation in VRAM2 and VRAMS or not 127 // if (vchanges[5] != 0) 6th pattern in VRAM2 must be updated 128 129 #define scanline (*p_scanline) 130 131 extern UInt32 *p_scanline; 132 // The current rendered line on screen 133 134 extern UChar *PCM; 135 // The ADPCM array (0x10000 bytes) 136 137 //! A pointer to know where we're currently reading data in the cd buffer 138 extern UChar *cd_sector_buffer; 139 140 //! The real buffer into which data are written from the cd and in which we 141 //! takes data to gives it back throught the cd ports 142 extern UChar *cd_read_buffer; 143 144 //! extra ram provided by the system CD card 145 extern UChar *cd_extra_mem; 146 147 //! extra ram provided by the super system CD card 148 extern UChar *cd_extra_super_mem; 149 150 //! extra ram provided by the Arcade card 151 extern UChar *ac_extra_mem; 152 153 //! remaining useful data in cd_read_buffer 154 extern UInt32 pce_cd_read_datacnt; 155 156 //! number of sectors we must still read on cd 157 extern UChar cd_sectorcnt; 158 159 //! number of the current command of the cd interface 160 extern UChar pce_cd_curcmd; 161 162 extern UChar* zp_base; 163 // pointer to the beginning of the Zero Page area 164 165 extern UChar* sp_base; 166 // pointer to the beginning of the Stack Area 167 168 extern UChar* mmr; 169 // Value of each of the MMR registers 170 171 extern UChar *IOAREA; 172 // physical address on emulator machine of the IO area (fake address as it has to be handled specially) 173 174 //! 175 extern UChar *PageR[8]; 176 extern UChar *ROMMapR[256]; 177 178 extern UChar *PageW[8]; 179 extern UChar *ROMMapW[256]; 180 181 //! False "ram"s in which you can read/write (to homogeneize writes into RAM, BRAM, ... as well as in rom) but the result isn't coherent 182 extern UChar* trap_ram_read; 183 extern UChar* trap_ram_write; 184 185 // physical address on emulator machine of each of the 256 banks 186 187 #define cyclecount (*p_cyclecount) 188 189 extern UInt32 *p_cyclecount; 190 // Number of elapsed cycles 191 192 #define cyclecountold (*p_cyclecountold) 193 194 extern UInt32 *p_cyclecountold; 195 // Previous number of elapsed cycles 196 197 #define external_control_cpu (*p_external_control_cpu) 198 199 extern SInt32 *p_external_control_cpu; 200 201 extern const UInt32 TimerPeriod; 202 // Base period for the timer 203 204 // registers: 205 206 #if defined(SHARED_MEMORY) 207 208 #define reg_pc (*p_reg_pc) 209 #define reg_a (*p_reg_a) 210 #define reg_x (*p_reg_x) 211 #define reg_y (*p_reg_y) 212 #define reg_p (*p_reg_p) 213 #define reg_s (*p_reg_s) 214 215 extern UInt16 *p_reg_pc; 216 extern UChar *p_reg_a; 217 extern UChar *p_reg_x; 218 extern UChar *p_reg_y; 219 extern UChar *p_reg_p; 220 extern UChar *p_reg_s; 221 222 #else 223 extern UInt16 reg_pc; 224 extern UChar reg_a; 225 extern UChar reg_x; 226 extern UChar reg_y; 227 extern UChar reg_p; 228 extern UChar reg_s; 229 #endif 230 231 // These are the main h6280 register, reg_p is the flag register 232 233 #define cycles (*p_cycles) 234 235 extern UInt32 *p_cycles; 236 // Number of pc engine cycles elapsed since the resetting of the emulated console 237 238 /** 239 * Definitions to ease writing 240 **/ 241 242 #define VRR 2 243 enum _VDC_REG { 244 MAWR, /* 0 */ /* Memory Address Write Register */ 245 MARR, /* 1 */ /* Memory Adress Read Register */ 246 VWR, /* 2 */ /* VRAM Read Register / VRAM Write Register */ 247 vdc3, /* 3 */ 248 vdc4, /* 4 */ 249 CR, /* 5 */ /* Control Register */ 250 RCR, /* 6 */ /* Raster Compare Register */ 251 BXR, /* 7 */ /* Horizontal scroll offset */ 252 BYR, /* 8 */ /* Vertical scroll offset */ 253 MWR, /* 9 */ /* Memory Width Register */ 254 HSR, /* A */ /* Unknown, other horizontal definition */ 255 HDR, /* B */ /* Horizontal Definition */ 256 VPR, /* C */ /* Higher byte = VDS, lower byte = VSW */ 257 VDW, /* D */ /* Vertical Definition */ 258 VCR, /* E */ /* Vertical counter between restarting of display*/ 259 DCR, /* F */ /* DMA Control */ 260 SOUR, /* 10 */ /* Source Address of DMA transfert */ 261 DISTR,/* 11 */ /* Destination Address of DMA transfert */ 262 LENR, /* 12 */ /* Length of DMA transfert */ 263 SATB /* 13 */ /* Adress of SATB */ 264 }; 265 266 #define NODATA 0xff 267 #define ENABLE 1 268 #define DISABLE 0 269 270 #define AC_ENABLE_OFFSET_BASE_6 0x40 271 #define AC_ENABLE_OFFSET_BASE_A 0x20 272 #define AC_INCREMENT_BASE 0x10 273 #define AC_USE_OFFSET 0x02 274 #define AC_ENABLE_INC 0x01 275 276 #endif 277