1 /**************************************************************************** 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2014 QLogic Corporation 22 * The contents of this file are subject to the terms of the 23 * QLogic End User License (the "License"). 24 * You may not use this file except in compliance with the License. 25 * 26 * You can obtain a copy of the License at 27 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/ 28 * QLogic_End_User_Software_License.txt 29 * See the License for the specific language governing permissions 30 * and limitations under the License. 31 * 32 * 33 * Name: aeu_inputs.h 34 * 35 * Description: This file contains the AEU inputs bits definitions which 36 * should be used to configure the MISC_REGISTERS_AEU_ENABLE 37 * registers. 38 * The file was based upon the AEU specification. 39 * 40 * Created: 10/19/2006 eilong 41 * 42 * $Date: 2014/01/02 $ $Revision: #18 $ 43 ****************************************************************************/ 44 #ifndef AEU_INPUTS_H 45 #define AEU_INPUTS_H 46 47 48 // AEU INPUT REGISTER 1 49 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION0 (0x1<<0)// Type: Event, Required Destination: MCP/Driver0 50 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION1 (0x1<<1)// Type: Event, Required Destination: MCP/Driver1 51 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)// Type: Event, Required Destination: MCP 52 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_0 (0x1<<3)// Type: Event, Required Destination: MCP 53 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_0 (0x1<<4)// Type: Event, Required Destination: MCP 54 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)// Type: Event, Required Destination: MCP 55 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_1 (0x1<<6)// Type: Event, Required Destination: MCP 56 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_1 (0x1<<7)// Type: Event, Required Destination: MCP 57 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_1 (0x1<<8)// Type: Event, Required Destination: MCP 58 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)// Type: Event, Required Destination: MCP 59 #define AEU_INPUTS_ATTN_BITS_VPD_EVENT_FUNCTION0 (0x1<<10)// Type: Event, Required Destination: MCP 60 #define AEU_INPUTS_ATTN_BITS_VPD_EVENT_FUNCTION1 (0x1<<11)// Type: Event, Required Destination: MCP 61 #define AEU_INPUTS_ATTN_BITS_EXPANSION_ROM_EVENT0 (0x1<<12)// Type: Event, Required Destination: MCP 62 #define AEU_INPUTS_ATTN_BITS_EXPANSION_ROM_EVENT1 (0x1<<13)// Type: Event, Required Destination: MCP 63 #define AEU_INPUTS_ATTN_BITS_SPIO4 (0x1<<14)// Type: Attention, Required Destination: MCP/Driver0/Driver1 64 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)// Type: Attention, Required Destination: MCP/Driver0/Driver1 65 #define AEU_INPUTS_ATTN_BITS_MSI_X_INDICATION_FOR_FUNCTION_0 (0x1<<16)// Type: Event, Required Destination: MCP/Driver0 66 #define AEU_INPUTS_ATTN_BITS_MSI_X_INDICATION_FOR_FUNCTION_1 (0x1<<17)// Type: Event, Required Destination: MCP/Driver1 67 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)// Type: Attention, Required Destination: MCP/Driver0/Driver1 68 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)// Type: Attention, Required Destination: MCP/Driver0/Driver1 69 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)// Type: Attention, Required Destination: MCP/Driver0/Driver1 70 #define AEU_INPUTS_ATTN_BITS_PARSER_HW_INTERRUPT (0x1<<21)// Type: Attention, Required Destination: MCP/Driver0/Driver1 71 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)// Type: Attention, Required Destination: MCP/Driver0/Driver1 72 #define AEU_INPUTS_ATTN_BITS_SEARCHER_HW_INTERRUPT (0x1<<23)// Type: Attention, Required Destination: MCP/Driver0/Driver1 73 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)// Type: Attention, Required Destination: MCP/Driver0/Driver1 74 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)// Type: Attention, Required Destination: MCP/Driver0/Driver1 75 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)// Type: Attention, Required Destination: MCP/Driver0/Driver1 76 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)// Type: Attention, Required Destination: MCP/Driver0/Driver1 77 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)// Type: Attention, Required Destination: MCP/Driver0/Driver1 78 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)// Type: Attention, Required Destination: MCP/Driver0/Driver1 79 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)// Type: Attention, Required Destination: MCP/Driver0/Driver1 80 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)// Type: Attention, Required Destination: MCP/Driver0/Driver1 81 82 83 84 #define HW_INTERRUT_ASSERT_SET_0 \ 85 ( AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\ 86 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\ 87 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\ 88 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\ 89 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 90 91 92 #define HW_PRTY_ASSERT_SET_0 \ 93 ( AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\ 94 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\ 95 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\ 96 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 97 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 98 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 99 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 100 101 102 // AEU INPUT REGISTER 2 103 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)// Type: Attention, Required Destination: MCP/Driver0/Driver1 104 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (0x1<<1)// Type: Attention, Required Destination: MCP/Driver0/Driver1 105 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)// Type: Attention, Required Destination: MCP/Driver0/Driver1 106 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)// Type: Attention, Required Destination: MCP/Driver0/Driver1 107 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)// Type: Attention, Required Destination: MCP/Driver0/Driver1 108 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)// Type: Attention, Required Destination: MCP/Driver0/Driver1 109 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)// Type: Attention, Required Destination: MCP/Driver0/Driver1 110 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)// Type: Attention, Required Destination: MCP/Driver0/Driver1 111 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)// Type: Attention, Required Destination: MCP/Driver0/Driver1 112 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)// Type: Attention, Required Destination: MCP/Driver0/Driver1 113 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)// Type: Attention, Required Destination: MCP/Driver0/Driver1 114 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)// Type: Attention, Required Destination: MCP/Driver0/Driver1 115 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)// Type: Attention, Required Destination: MCP/Driver0/Driver1 116 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)// Type: Attention, Required Destination: MCP/Driver0/Driver1 117 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)// Type: Attention, Required Destination: MCP/Driver0/Driver1 118 #define AEU_INPUTS_ATTN_BITS_NIG_HW_INTERRUPT (0x1<<15)// Type: Attention, Required Destination: MCP/Driver0/Driver1 119 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)// Type: Attention, Required Destination: MCP/Driver0/Driver1 120 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_HW_INTERRUPT (0x1<<17)// Type: Attention, Required Destination: MCP/Driver0/Driver1 121 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)// Type: Attention, Required Destination: MCP/Driver0/Driver1 122 #define AEU_INPUTS_ATTN_BITS_DEBUG_HW_INTERRUPT (0x1<<19)// Type: Attention, Required Destination: MCP/Driver0/Driver1 123 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)// Type: Attention, Required Destination: MCP/Driver0/Driver1 124 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)// Type: Attention, Required Destination: MCP/Driver0/Driver1 125 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)// Type: Attention, Required Destination: MCP/Driver0/Driver1 126 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)// Type: Attention, Required Destination: MCP/Driver0/Driver1 127 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)// Type: Attention, Required Destination: MCP/Driver0/Driver1 128 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)// Type: Attention, Required Destination: MCP/Driver0/Driver1 129 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)// Type: Attention, Required Destination: MCP/Driver0/Driver1 130 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)// Type: Attention, Required Destination: MCP/Driver0/Driver1 131 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)// Type: Attention, Required Destination: MCP/Driver0/Driver1 132 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)// Type: Attention, Required Destination: MCP/Driver0/Driver1 133 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)// Type: Attention, Required Destination: MCP/Driver0/Driver1 134 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)// Type: Attention, Required Destination: MCP/Driver0/Driver1 135 136 #define HW_INTERRUT_ASSERT_SET_1 \ 137 ( AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\ 138 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\ 139 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\ 140 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\ 141 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\ 142 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\ 143 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\ 144 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\ 145 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\ 146 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\ 147 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 148 149 #define HW_PRTY_ASSERT_SET_1 \ 150 ( AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 151 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\ 152 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 153 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\ 154 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 155 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\ 156 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 157 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 158 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 159 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\ 160 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\ 161 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 162 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\ 163 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\ 164 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 165 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 166 167 168 // AEU INPUT REGISTER 3 169 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)// Type: Attention, Required Destination: MCP/Driver0/Driver1 170 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)// Type: Attention, Required Destination: MCP/Driver0/Driver1 171 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)// Type: Attention, Required Destination: MCP/Driver0/Driver1 172 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)// Type: Attention, Required Destination: MCP/Driver0/Driver1 173 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)// Type: Attention, Required Destination: MCP/Driver0/Driver1 174 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)// Type: Attention, Required Destination: MCP/Driver0/Driver1 175 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)// Type: Attention, Required Destination: MCP/Driver0/Driver1 176 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)// Type: Attention, Required Destination: MCP/Driver0/Driver1 177 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)// Type: Attention, Required Destination: MCP/Driver0/Driver1 178 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)// Type: Attention, Required Destination: MCP/Driver0/Driver1 179 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)// Type: Attention, Required Destination: MCP/Driver0/Driver1 180 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)// Type: Attention, Required Destination: MCP/Driver0/Driver1 181 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)// Type: Attention, Required Destination: MCP/Driver0/Driver1 182 #define AEU_INPUTS_ATTN_BITS_IGU_HW_INT_AND_MSI_X_CONF_CHANGE (0x1<<13)// Type: Attention, Required Destination: MCP/Driver0/Driver1 183 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)// Type: Attention, Required Destination: MCP/Driver0/Driver1 184 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)// Type: Attention, Required Destination: MCP/Driver0/Driver1 185 #define AEU_INPUTS_ATTN_BITS_PXP_PXP_MISC_MPS_ATTN (0x1<<16)// Type: Attention, Required Destination: MCP 186 #define AEU_INPUTS_ATTN_BITS_FLASH_INTERFACE_FLASH_EVENT (0x1<<17)// Type: Event, Required Destination: MCP 187 #define AEU_INPUTS_ATTN_BITS_SMB_INTERFACE_SMB_EVENT (0x1<<18)// Type: Event, Required Destination: MCP 188 #define AEU_INPUTS_ATTN_BITS_MCP_MAPPED_REGISTERS_MCP_ATTN0 (0x1<<19)// Type: Event, Required Destination: MCP 189 #define AEU_INPUTS_ATTN_BITS_MCP_MAPPED_REGISTERS_MCP_ATTN1 (0x1<<20)// Type: Event, Required Destination: MCP 190 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_1_FUNC0 (0x1<<21)// Type: Event, Required Destination: MCP 191 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_2_FUNC0 (0x1<<22)// Type: Event, Required Destination: MCP 192 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_3_FUNC0 (0x1<<23)// Type: Event, Required Destination: MCP 193 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_4_FUNC0 (0x1<<24)// Type: Event, Required Destination: MCP 194 #define AEU_INPUTS_ATTN_BITS_MISC_PERST (0x1<<25)// Type: Event, Required Destination: MCP 195 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_1_FUNC1 (0x1<<26)// Type: Event, Required Destination: MCP 196 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_2_FUNC1 (0x1<<27)// Type: Event, Required Destination: MCP 197 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_3_FUNC1 (0x1<<28)// Type: Event, Required Destination: MCP 198 #define AEU_INPUTS_ATTN_BITS_SW_TIMERS_ATTN_4_FUNC1 (0x1<<29)// Type: Event, Required Destination: MCP 199 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN0 (0x1<<30)// Type: Attention, Required Destination: MCP/Driver0/Driver1 200 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN1 (0x1<<31)// Type: Attention, Required Destination: MCP/Driver0/Driver1 201 202 203 204 #define HW_INTERRUT_ASSERT_SET_2 \ 205 ( AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\ 206 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\ 207 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\ 208 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\ 209 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\ 210 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 211 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 212 213 /*AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\*/ 214 215 #define HW_PRTY_ASSERT_SET_2 \ 216 ( AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\ 217 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\ 218 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 219 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\ 220 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\ 221 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 222 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\ 223 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 224 225 226 #define HW_PRTY_ASSERT_SET_3 \ 227 ( AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 228 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 229 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 230 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 231 232 233 // AEU INPUT REGISTER 4 234 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN2 (0x1<<0)// Type: Attention, Required Destination: MCP/Driver0/Driver1 235 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN3 (0x1<<1)// Type: Attention, Required Destination: MCP/Driver0/Driver1 236 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN4 (0x1<<2)// Type: Attention, Required Destination: MCP/Driver0/Driver1 237 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN5 (0x1<<3)// Type: Attention, Required Destination: MCP/Driver0/Driver1 238 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN6 (0x1<<4)// Type: Attention, Required Destination: MCP/Driver0/Driver1 239 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN7 (0x1<<5)// Type: Attention, Required Destination: MCP/Driver0/Driver1 240 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN8 (0x1<<6)// Type: Attention, Required Destination: MCP/Driver0/Driver1 241 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN9 (0x1<<7)// Type: Attention, Required Destination: MCP/Driver0/Driver1 242 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN10 (0x1<<8)// Type: Attention, Required Destination: MCP/Driver0/Driver1 243 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN11 (0x1<<9)// Type: Attention, Required Destination: MCP/Driver0/Driver1 244 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN12 (0x1<<10)// Type: Attention, Required Destination: MCP/Driver0/Driver1 245 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN13 (0x1<<11)// Type: Attention, Required Destination: MCP/Driver0/Driver1 246 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN14 (0x1<<12)// Type: Attention, Required Destination: MCP/Driver0/Driver1 247 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN15 (0x1<<13)// Type: Attention, Required Destination: MCP/Driver0/Driver1 248 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN16 (0x1<<14)// Type: Attention, Required Destination: MCP/Driver0/Driver1 249 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN17 (0x1<<15)// Type: Attention, Required Destination: MCP/Driver0/Driver1 250 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN18 (0x1<<16)// Type: Attention, Required Destination: MCP/Driver0/Driver1 251 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN19 (0x1<<17)// Type: Attention, Required Destination: MCP/Driver0/Driver1 252 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN20 (0x1<<18)// Type: Attention, Required Destination: MCP/Driver0/Driver1 253 #define AEU_INPUTS_ATTN_BITS_GRC_MAPPED_GENERAL_ATTN21 (0x1<<19)// Type: Attention, Required Destination: MCP/Driver0/Driver1 254 #define AEU_INPUTS_ATTN_BITS_INIT_BLOCK_MAIN_POWER_INTERRUPT (0x1<<20)// Type: Event, Required Destination: MCP 255 #define AEU_INPUTS_ATTN_BITS_RBCR_LATCHED_ATTN (0x1<<21)// Type: Attention, Required Destination: MCP/Driver0/Driver1 256 #define AEU_INPUTS_ATTN_BITS_RBCT_LATCHED_ATTN (0x1<<22)// Type: Attention, Required Destination: MCP/Driver0/Driver1 257 #define AEU_INPUTS_ATTN_BITS_RBCN_LATCHED_ATTN (0x1<<23)// Type: Attention, Required Destination: MCP/Driver0/Driver1 258 #define AEU_INPUTS_ATTN_BITS_RBCU_LATCHED_ATTN (0x1<<24)// Type: Attention, Required Destination: MCP/Driver0/Driver1 259 #define AEU_INPUTS_ATTN_BITS_RBCP_LATCHED_ATTN (0x1<<25)// Type: Attention, Required Destination: MCP/Driver0/Driver1 260 #define AEU_INPUTS_ATTN_BITS_GRC_LATCHED_TIMEOUT_ATTENTION (0x1<<26)// Type: Attention, Required Destination: MCP/Driver0/Driver1 261 #define AEU_INPUTS_ATTN_BITS_GRC_LATCHED_RESERVED_ACCESS_ATTN (0x1<<27)// Type: Attention, Required Destination: MCP/Driver0/Driver1 262 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)// Type: Attention, Required Destination: MCP/Driver0/Driver1 263 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)// Type: Attention, Required Destination: MCP/Driver0/Driver1 264 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)// Type: Attention, Required Destination: MCP/Driver0/Driver1 265 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)// Type: Attention, Required Destination: MCP/Driver0/Driver1 266 267 // AEU INPUT REGISTER 5 268 #define AEU_INPUTS_ATTN_BITS_PGLUE_CFG_SPACE_ATTN (0x1<<0)// Type: Attention, Required Destination: MCP 269 #define AEU_INPUTS_ATTN_BITS_PGLUE_FLR_ATTN (0x1<<1)// Type: Attention, Required Destination: MCP 270 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)// Type: Attention, Required Destination: MCP/Driver0/Driver1 271 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)// Type: Attention, Required Destination: MCP/Driver0/Driver1 272 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)// Type: Attention, Required Destination: MCP/Driver0/Driver1 273 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)// Type: Attention, Required Destination: MCP/Driver0/Driver1 274 275 #define HW_INTERRUT_ASSERT_SET_4 \ 276 ( AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT |\ 277 AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) 278 279 #define HW_PRTY_ASSERT_SET_4 \ 280 ( AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\ 281 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 282 283 #endif //AEU_INPUTS_H 284