1 /* $OpenBSD: aic7xxxvar.h,v 1.40 2024/05/29 01:11:53 jsg Exp $ */ 2 /* 3 * Core definitions and data structures shareable across OS platforms. 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2001 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: aic7xxxvar.h,v 1.40 2024/05/29 01:11:53 jsg Exp $ 42 * 43 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.50 2003/12/17 00:02:09 gibbs Exp $ 44 */ 45 /* 46 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 47 */ 48 49 #ifndef _AIC7XXXVAR_H_ 50 #define _AIC7XXXVAR_H_ 51 52 /* Register Definitions */ 53 #include <dev/microcode/aic7xxx/aic7xxx_reg.h> 54 55 #include <dev/ic/aic7xxx_cam.h> 56 /************************* Forward Declarations *******************************/ 57 struct seeprom_descriptor; 58 59 /****************************** Useful Macros *********************************/ 60 #ifndef MAX 61 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 62 #endif 63 64 #ifndef MIN 65 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 66 #endif 67 68 #ifndef TRUE 69 #define TRUE 1 70 #endif 71 #ifndef FALSE 72 #define FALSE 0 73 #endif 74 75 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 76 77 #define ALL_CHANNELS '\0' 78 #define ALL_TARGETS_MASK 0xFFFF 79 #define INITIATOR_WILDCARD (~0) 80 81 #define SCSIID_TARGET(ahc, scsiid) \ 82 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 83 >> TID_SHIFT) 84 #define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86 #define SCSIID_CHANNEL(ahc, scsiid) \ 87 ((((ahc)->features & AHC_TWIN) != 0) \ 88 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 89 : 'A') 90 #define SCB_IS_SCSIBUS_B(ahc, scb) \ 91 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 92 #define SCB_GET_OUR_ID(scb) \ 93 SCSIID_OUR_ID((scb)->hscb->scsiid) 94 #define SCB_GET_TARGET(ahc, scb) \ 95 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 96 #define SCB_GET_CHANNEL(ahc, scb) \ 97 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 98 #define SCB_GET_LUN(scb) \ 99 ((scb)->hscb->lun & LID) 100 #define SCB_GET_TARGET_OFFSET(ahc, scb) \ 101 (SCB_GET_TARGET(ahc, scb)) 102 #define SCB_GET_TARGET_MASK(ahc, scb) \ 103 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 104 #ifdef AHC_DEBUG 105 #define SCB_IS_SILENT(scb) \ 106 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 107 && (((scb)->flags & SCB_SILENT) != 0)) 108 #else 109 #define SCB_IS_SILENT(scb) \ 110 (((scb)->flags & SCB_SILENT) != 0) 111 #endif 112 #define TCL_TARGET_OFFSET(tcl) \ 113 ((((tcl) >> 4) & TID) >> 4) 114 #define TCL_LUN(tcl) \ 115 (tcl & (AHC_NUM_LUNS - 1)) 116 #define BUILD_TCL(scsiid, lun) \ 117 ((lun) | (((scsiid) & TID) << 4)) 118 119 #ifndef AHC_TARGET_MODE 120 #undef AHC_TMODE_ENABLE 121 #define AHC_TMODE_ENABLE 0 122 #endif 123 124 /**************************** Driver Constants ********************************/ 125 /* 126 * The maximum number of supported targets. 127 */ 128 #define AHC_NUM_TARGETS 16 129 130 /* 131 * The maximum number of supported luns. 132 * The identify message only supports 64 luns in SPI3. 133 * You can have 2^64 luns when information unit transfers are enabled, 134 * but it is doubtful this driver will ever support IUTs. 135 */ 136 #define AHC_NUM_LUNS 64 137 138 /* 139 * The maximum transfer per S/G segment. 140 * Limited by MAXPHYS or a 24-bit counter. 141 */ 142 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff) 143 144 /* 145 * The maximum amount of SCB storage in hardware on a controller. 146 * This value represents an upper bound. Controllers vary in the number 147 * they actually support. 148 */ 149 #define AHC_SCB_MAX 255 150 151 /* 152 * The maximum number of concurrent transactions supported per driver instance. 153 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 154 * the space for SCBs on the host adapter varies by model, the driver will 155 * page the SCBs between host and controller memory as needed. We are limited 156 * to 253 because: 157 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 158 * 2) We reserve one value, 255, to represent the invalid element. 159 * 3) Our input queue scheme requires one SCB to always be reserved 160 * in advance of queuing any SCBs. This takes us down to 254. 161 * 4) To handle our output queue correctly on machines that only 162 * support 32bit stores, we must clear the array 4 bytes at a 163 * time. To avoid colliding with a DMA write from the sequencer, 164 * we must be sure that 4 slots are empty when we write to clear 165 * the queue. This reduces us to 253 SCBs: 1 that just completed 166 * and the known three additional empty slots in the queue that 167 * precede it. 168 */ 169 #define AHC_MAX_QUEUE 253 170 171 /* 172 * The maximum amount of SCB storage we allocate in host memory. This 173 * number should reflect the 1 additional SCB we require to handle our 174 * qinfifo mechanism. 175 */ 176 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 177 178 /* 179 * Ring Buffer of incoming target commands. 180 * We allocate 256 to simplify the logic in the sequencer 181 * by using the natural wrap point of an 8bit counter. 182 */ 183 #define AHC_TMODE_CMDS 256 184 185 /* Reset line assertion time in us */ 186 #define AHC_BUSRESET_DELAY 25 187 188 /******************* Chip Characteristics/Operating Settings *****************/ 189 /* 190 * Chip Type 191 * The chip order is from least sophisticated to most sophisticated. 192 */ 193 typedef enum { 194 AHC_NONE = 0x0000, 195 AHC_CHIPID_MASK = 0x00FF, 196 AHC_AIC7770 = 0x0001, 197 AHC_AIC7850 = 0x0002, 198 AHC_AIC7855 = 0x0003, 199 AHC_AIC7859 = 0x0004, 200 AHC_AIC7860 = 0x0005, 201 AHC_AIC7870 = 0x0006, 202 AHC_AIC7880 = 0x0007, 203 AHC_AIC7895 = 0x0008, 204 AHC_AIC7895C = 0x0009, 205 AHC_AIC7890 = 0x000a, 206 AHC_AIC7896 = 0x000b, 207 AHC_AIC7892 = 0x000c, 208 AHC_AIC7899 = 0x000d, 209 AHC_VL = 0x0100, /* Bus type VL */ 210 AHC_EISA = 0x0200, /* Bus type EISA */ 211 AHC_PCI = 0x0400, /* Bus type PCI */ 212 AHC_BUS_MASK = 0x0F00 213 } ahc_chip; 214 215 /* 216 * Features available in each chip type. 217 */ 218 typedef enum { 219 AHC_FENONE = 0x00000, 220 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 221 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 222 AHC_WIDE = 0x00004, /* Wide Channel */ 223 AHC_TWIN = 0x00008, /* Twin Channel */ 224 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 225 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 226 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 227 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 228 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 229 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 230 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 231 AHC_DT = 0x00800, /* Double Transition transfers */ 232 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 233 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 234 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 235 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 236 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 237 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 238 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 239 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 240 AHC_AIC7770_FE = AHC_FENONE, 241 /* 242 * The real 7850 does not support Ultra modes, but there are 243 * several cards that use the generic 7850 PCI ID even though 244 * they are using an Ultra capable chip (7859/7860). We start 245 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 246 * register to determine if the capability is really present. 247 */ 248 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 249 AHC_AIC7860_FE = AHC_AIC7850_FE, 250 AHC_AIC7870_FE = AHC_TARGETMODE|AHC_AUTOPAUSE, 251 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 252 /* 253 * Although we have space for both the initiator and 254 * target roles on ULTRA2 chips, we currently disable 255 * the initiator role to allow multi-scsi-id target mode 256 * configurations. We can only respond on the same SCSI 257 * ID as our initiator role if we allow initiator operation. 258 * At some point, we should add a configuration knob to 259 * allow both roles to be loaded. 260 */ 261 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 262 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 263 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 264 |AHC_TARGETMODE, 265 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 266 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 267 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 268 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 269 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 270 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 271 } ahc_feature; 272 273 /* 274 * Bugs in the silicon that we work around in software. 275 */ 276 typedef enum { 277 AHC_BUGNONE = 0x00, 278 /* 279 * On all chips prior to the U2 product line, 280 * the WIDEODD S/G segment feature does not 281 * work during scsi->HostBus transfers. 282 */ 283 AHC_TMODE_WIDEODD_BUG = 0x01, 284 /* 285 * On the aic7890/91 Rev 0 chips, the autoflush 286 * feature does not work. A manual flush of 287 * the DMA FIFO is required. 288 */ 289 AHC_AUTOFLUSH_BUG = 0x02, 290 /* 291 * On many chips, cacheline streaming does not work. 292 */ 293 AHC_CACHETHEN_BUG = 0x04, 294 /* 295 * On the aic7896/97 chips, cacheline 296 * streaming must be enabled. 297 */ 298 AHC_CACHETHEN_DIS_BUG = 0x08, 299 /* 300 * PCI 2.1 Retry failure on non-empty data fifo. 301 */ 302 AHC_PCI_2_1_RETRY_BUG = 0x10, 303 /* 304 * Controller does not handle cacheline residuals 305 * properly on S/G segments if PCI MWI instructions 306 * are allowed. 307 */ 308 AHC_PCI_MWI_BUG = 0x20, 309 /* 310 * An SCB upload using the SCB channel's 311 * auto array entry copy feature may 312 * corrupt data. This appears to only 313 * occur on 66MHz systems. 314 */ 315 AHC_SCBCHAN_UPLOAD_BUG = 0x40 316 } ahc_bug; 317 318 /* 319 * Configuration specific settings. 320 * The driver determines these settings by probing the 321 * chip/controller's configuration. 322 */ 323 typedef enum { 324 AHC_FNONE = 0x000, 325 AHC_PRIMARY_CHANNEL = 0x003, /* 326 * The channel that should 327 * be probed first. 328 */ 329 AHC_USEDEFAULTS = 0x004, /* 330 * For cards without an seeprom 331 * or a BIOS to initialize the chip's 332 * SRAM, we use the default target 333 * settings. 334 */ 335 AHC_SEQUENCER_DEBUG = 0x008, 336 AHC_SHARED_SRAM = 0x010, 337 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 338 AHC_RESET_BUS_A = 0x040, 339 AHC_RESET_BUS_B = 0x080, 340 AHC_EXTENDED_TRANS_A = 0x100, 341 AHC_EXTENDED_TRANS_B = 0x200, 342 AHC_TERM_ENB_A = 0x400, 343 AHC_TERM_ENB_B = 0x800, 344 AHC_INITIATORROLE = 0x1000, /* 345 * Allow initiator operations on 346 * this controller. 347 */ 348 AHC_TARGETROLE = 0x2000, /* 349 * Allow target operations on this 350 * controller. 351 */ 352 AHC_NEWEEPROM_FMT = 0x4000, 353 AHC_RESOURCE_SHORTAGE = 0x8000, 354 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 355 AHC_INT50_SPEEDFLEX = 0x20000, /* 356 * Internal 50pin connector 357 * sits behind an aic3860 358 */ 359 AHC_SCB_BTT = 0x40000, /* 360 * The busy targets table is 361 * stored in SCB space rather 362 * than SRAM. 363 */ 364 AHC_BIOS_ENABLED = 0x80000, 365 AHC_ALL_INTERRUPTS = 0x100000, 366 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 367 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 368 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 369 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 370 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 371 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 372 AHC_DISABLE_PCI_PERR = 0x10000000, 373 AHC_HAS_TERM_LOGIC = 0x20000000, 374 AHC_SHUTDOWN_RECOVERY = 0x40000000 /* Terminate recovery thread. */ 375 } ahc_flag; 376 377 /************************* Hardware SCB Definition ***************************/ 378 379 /* 380 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 381 * consists of a "hardware SCB" mirroring the fields available on the card 382 * and additional information the kernel stores for each transaction. 383 * 384 * To minimize space utilization, a portion of the hardware scb stores 385 * different data during different portions of a SCSI transaction. 386 * As initialized by the host driver for the initiator role, this area 387 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 388 * the cdb has been presented to the target, this area serves to store 389 * residual transfer information and the SCSI status byte. 390 * For the target role, the contents of this area do not change, but 391 * still serve a different purpose than for the initiator role. See 392 * struct target_data for details. 393 */ 394 395 /* 396 * Status information embedded in the shared portion of 397 * an SCB after passing the cdb to the target. The kernel 398 * driver will only read this data for transactions that 399 * complete abnormally (non-zero status byte). 400 */ 401 struct status_pkt { 402 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 403 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 404 uint8_t scsi_status; /* Standard SCSI status byte */ 405 }; 406 407 /* 408 * Target mode version of the shared data SCB segment. 409 */ 410 struct target_data { 411 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 412 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 413 uint8_t scsi_status; /* SCSI status to give to initiator */ 414 uint8_t target_phases; /* Bitmap of phases to execute */ 415 uint8_t data_phase; /* Data-In or Data-Out */ 416 uint8_t initiator_tag; /* Initiator's transaction tag */ 417 }; 418 419 struct hardware_scb { 420 /*0*/ union { 421 /* 422 * If the cdb is 12 bytes or less, we embed it directly 423 * in the SCB. For longer cdbs, we embed the address 424 * of the cdb payload as seen by the chip and a DMA 425 * is used to pull it in. 426 */ 427 uint8_t cdb[12]; 428 uint32_t cdb_ptr; 429 struct status_pkt status; 430 struct target_data tdata; 431 } shared_data; 432 /* 433 * A word about residuals. 434 * The scb is presented to the sequencer with the dataptr and datacnt 435 * fields initialized to the contents of the first S/G element to 436 * transfer. The sgptr field is initialized to the bus address for 437 * the S/G element that follows the first in the in core S/G array 438 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 439 * S/G entry for this transfer (single S/G element transfer with the 440 * first elements address and length preloaded in the dataptr/datacnt 441 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 442 * The SG_FULL_RESID flag ensures that the residual will be correctly 443 * noted even if no data transfers occur. Once the data phase is entered, 444 * the residual sgptr and datacnt are loaded from the sgptr and the 445 * datacnt fields. After each S/G element's dataptr and length are 446 * loaded into the hardware, the residual sgptr is advanced. After 447 * each S/G element is expired, its datacnt field is checked to see 448 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 449 * residual sg ptr and the transfer is considered complete. If the 450 * sequencer determines that there is a residual in the transfer, it 451 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into 452 * host memory. To summarize: 453 * 454 * Sequencer: 455 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 456 * or residual_sgptr does not have SG_LIST_NULL set. 457 * 458 * o We are transferring the last segment if residual_datacnt has 459 * the SG_LAST_SEG flag set. 460 * 461 * Host: 462 * o A residual has occurred if a completed scb has the 463 * SG_RESID_VALID flag set. 464 * 465 * o residual_sgptr and sgptr refer to the "next" sg entry 466 * and so may point beyond the last valid sg entry for the 467 * transfer. 468 */ 469 /*12*/ uint32_t dataptr; 470 /*16*/ uint32_t datacnt; /* 471 * Byte 3 (numbered from 0) of 472 * the datacnt is really the 473 * 4th byte in that data address. 474 */ 475 /*20*/ uint32_t sgptr; 476 #define SG_PTR_MASK 0xFFFFFFF8 477 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 478 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 479 /*26*/ uint8_t lun; 480 /*27*/ uint8_t tag; /* 481 * Index into our kernel SCB array. 482 * Also used as the tag for tagged I/O 483 */ 484 /*28*/ uint8_t cdb_len; 485 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 486 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 487 /*31*/ uint8_t next; /* 488 * Used for threading SCBs in the 489 * "Waiting for Selection" and 490 * "Disconnected SCB" lists down 491 * in the sequencer. 492 */ 493 /*32*/ uint8_t cdb32[32]; /* 494 * CDB storage for cdbs of size 495 * 13->32. We store them here 496 * because hardware scbs are 497 * allocated from DMA safe 498 * memory so we are guaranteed 499 * the controller can access 500 * this data. 501 */ 502 }; 503 504 /************************ Kernel SCB Definitions ******************************/ 505 /* 506 * Some fields of the SCB are OS dependent. Here we collect the 507 * definitions for elements that all OS platforms need to include 508 * in there SCB definition. 509 */ 510 511 /* 512 * Definition of a scatter/gather element as transferred to the controller. 513 * The aic7xxx chips only support a 24bit length. We use the top byte of 514 * the length to store additional address bits and a flag to indicate 515 * that a given segment terminates the transfer. This gives us an 516 * addressable range of 512GB on machines with 64bit PCI or with chips 517 * that can support dual address cycles on 32bit PCI busses. 518 */ 519 struct ahc_dma_seg { 520 uint32_t addr; 521 uint32_t len; 522 #define AHC_DMA_LAST_SEG 0x80000000 523 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000 524 #define AHC_SG_LEN_MASK 0x00FFFFFF 525 }; 526 527 struct sg_map_node { 528 bus_dmamap_t sg_dmamap; 529 bus_addr_t sg_physaddr; 530 bus_dma_segment_t sg_dmasegs; 531 int sg_nseg; 532 struct ahc_dma_seg* sg_vaddr; 533 SLIST_ENTRY(sg_map_node) links; 534 }; 535 536 struct ahc_pci_busdata { 537 pci_chipset_tag_t pc; 538 pcitag_t tag; 539 u_int dev; 540 u_int func; 541 pcireg_t class; 542 }; 543 544 /* 545 * The current state of this SCB. 546 */ 547 typedef enum { 548 SCB_FLAG_NONE = 0x0000, 549 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 550 * Another device was active 551 * during the first timeout for 552 * this SCB so we gave ourselves 553 * an additional timeout period 554 * in case it was hogging the 555 * bus. 556 */ 557 SCB_DEVICE_RESET = 0x0004, 558 SCB_SENSE = 0x0008, 559 SCB_CDB32_PTR = 0x0010, 560 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 561 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 562 SCB_ABORT = 0x0100, 563 SCB_UNTAGGEDQ = 0x0200, 564 SCB_ACTIVE = 0x0400, 565 SCB_TARGET_IMMEDIATE = 0x0800, 566 SCB_TRANSMISSION_ERROR = 0x1000,/* 567 * We detected a parity or CRC 568 * error that has effected the 569 * payload of the command. This 570 * flag is checked when normal 571 * status is returned to catch 572 * the case of a target not 573 * responding to our attempt 574 * to report the error. 575 */ 576 SCB_TARGET_SCB = 0x2000, 577 SCB_SILENT = 0x4000 /* 578 * Be quiet about transmission type 579 * errors. They are expected and we 580 * don't want to upset the user. This 581 * flag is typically used during DV. 582 */ 583 } scb_flag; 584 585 struct scb { 586 struct hardware_scb *hscb; 587 union { 588 SLIST_ENTRY(scb) sle; 589 TAILQ_ENTRY(scb) tqe; 590 } links; 591 LIST_ENTRY(scb) pending_links; 592 593 struct scsi_xfer *xs; 594 struct ahc_softc *ahc_softc; 595 scb_flag flags; 596 bus_dmamap_t dmamap; 597 struct sg_map_node *sg_map; 598 struct ahc_dma_seg *sg_list; 599 bus_addr_t sg_list_phys; 600 u_int sg_count;/* How full ahc_dma_seg is */ 601 }; 602 603 struct scb_data { 604 SLIST_HEAD(, scb) free_scbs; /* 605 * Pool of SCBs ready to be assigned 606 * commands to execute. 607 */ 608 struct scb *scbindex[256]; /* 609 * Mapping from tag to SCB. 610 * As tag identifiers are an 611 * 8bit value, we provide space 612 * for all possible tag values. 613 * Any lookups to entries at or 614 * above AHC_SCB_MAX_ALLOC will 615 * always fail. 616 */ 617 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 618 struct scb *scbarray; /* Array of kernel SCBs */ 619 struct scsi_sense_data *sense; /* Per SCB sense data */ 620 621 /* 622 * "Bus" addresses of our data structures. 623 */ 624 bus_dmamap_t hscb_dmamap; 625 bus_addr_t hscb_busaddr; 626 bus_dma_segment_t hscb_seg; 627 int hscb_nseg; 628 int hscb_size; 629 630 bus_dmamap_t sense_dmamap; 631 bus_addr_t sense_busaddr; 632 bus_dma_segment_t sense_seg; 633 int sense_nseg; 634 int sense_size; 635 636 SLIST_HEAD(, sg_map_node) sg_maps; 637 uint8_t numscbs; 638 uint8_t maxhscbs; /* Number of SCBs on the card */ 639 uint8_t init_level; /* 640 * How far we've initialized 641 * this structure. 642 */ 643 }; 644 645 /************************ Target Mode Definitions *****************************/ 646 647 /* 648 * Connection descriptor for select-in requests in target mode. 649 */ 650 struct target_cmd { 651 uint8_t scsiid; /* Our ID and the initiator's ID */ 652 uint8_t identify; /* Identify message */ 653 uint8_t bytes[22]; /* 654 * Bytes contains any additional message 655 * bytes terminated by 0xFF. The remainder 656 * is the cdb to execute. 657 */ 658 uint8_t cmd_valid; /* 659 * When a command is complete, the firmware 660 * will set cmd_valid to all bits set. 661 * After the host has seen the command, 662 * the bits are cleared. This allows us 663 * to just peek at host memory to determine 664 * if more work is complete. cmd_valid is on 665 * an 8 byte boundary to simplify setting 666 * it on aic7880 hardware which only has 667 * limited direct access to the DMA FIFO. 668 */ 669 uint8_t pad[7]; 670 }; 671 672 /* 673 * Number of events we can buffer up if we run out 674 * of immediate notify ccbs. 675 */ 676 #define AHC_TMODE_EVENT_BUFFER_SIZE 8 677 struct ahc_tmode_event { 678 uint8_t initiator_id; 679 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 680 #define EVENT_TYPE_BUS_RESET 0xFF 681 uint8_t event_arg; 682 }; 683 684 /* 685 * Per enabled lun target mode state. 686 * As this state is directly influenced by the host OS'es target mode 687 * environment, we let the OS module define it. Forward declare the 688 * structure here so we can store arrays of them, etc. in OS neutral 689 * data structures. 690 */ 691 #ifdef AHC_TARGET_MODE 692 struct ahc_tmode_lstate { 693 #if 0 694 struct cam_path *path; 695 struct ccb_hdr_slist accept_tios; 696 struct ccb_hdr_slist immed_notifies; 697 #endif 698 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 699 uint8_t event_r_idx; 700 uint8_t event_w_idx; 701 }; 702 #else 703 struct ahc_tmode_lstate; 704 #endif 705 706 /******************** Transfer Negotiation Datastructures *********************/ 707 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */ 708 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 709 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 710 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 711 712 #define AHC_WIDTH_UNKNOWN 0xFF 713 #define AHC_PERIOD_UNKNOWN 0xFF 714 #define AHC_OFFSET_UNKNOWN 0xFF 715 #define AHC_PPR_OPTS_UNKNOWN 0xFF 716 717 /* 718 * Transfer Negotiation Information. 719 */ 720 struct ahc_transinfo { 721 uint8_t protocol_version; /* SCSI Revision level */ 722 uint8_t transport_version; /* SPI Revision level */ 723 uint8_t width; /* Bus width */ 724 uint8_t period; /* Sync rate factor */ 725 uint8_t offset; /* Sync offset */ 726 uint8_t ppr_options; /* Parallel Protocol Request options */ 727 }; 728 729 /* 730 * Per-initiator current, goal and user transfer negotiation information. */ 731 struct ahc_initiator_tinfo { 732 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 733 struct ahc_transinfo curr; 734 struct ahc_transinfo goal; 735 struct ahc_transinfo user; 736 }; 737 738 /* 739 * Per enabled target ID state. 740 * Pointers to lun target state as well as sync/wide negotiation information 741 * for each initiator<->target mapping. For the initiator role we pretend 742 * that we are the target and the targets are the initiators since the 743 * negotiation is the same regardless of role. 744 */ 745 struct ahc_tmode_tstate { 746 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 747 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 748 749 /* 750 * Per initiator state bitmasks. 751 */ 752 uint16_t auto_negotiate;/* Auto Negotiation Required */ 753 uint16_t ultraenb; /* Using ultra sync rate */ 754 uint16_t discenable; /* Disconnection allowed */ 755 uint16_t tagenable; /* Tagged Queuing allowed */ 756 }; 757 758 /* 759 * Data structure for our table of allowed synchronous transfer rates. 760 */ 761 struct ahc_syncrate { 762 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 763 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 764 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 765 #define ST_SXFR 0x010 /* Rate Single Transition Only */ 766 #define DT_SXFR 0x040 /* Rate Double Transition Only */ 767 uint8_t period; /* Period to send to SCSI target */ 768 char *rate; 769 }; 770 771 /* Safe and valid period for async negotiations. */ 772 #define AHC_ASYNC_XFER_PERIOD 0x45 773 #define AHC_ULTRA2_XFER_PERIOD 0x0a 774 775 /* 776 * Indexes into our table of synchronous transfer rates. 777 */ 778 #define AHC_SYNCRATE_DT 0 779 #define AHC_SYNCRATE_ULTRA2 1 780 #define AHC_SYNCRATE_ULTRA 3 781 #define AHC_SYNCRATE_FAST 6 782 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 783 #define AHC_SYNCRATE_MIN 13 784 785 /***************************** Lookup Tables **********************************/ 786 /* 787 * Phase -> name and message out response 788 * to parity errors in each phase table. 789 */ 790 struct ahc_phase_table_entry { 791 uint8_t phase; 792 uint8_t mesg_out; /* Message response to parity errors */ 793 char *phasemsg; 794 }; 795 796 /************************** Serial EEPROM Format ******************************/ 797 798 struct seeprom_config { 799 /* 800 * Per SCSI ID Configuration Flags 801 */ 802 uint16_t device_flags[16]; /* words 0-15 */ 803 #define CFXFER 0x0007 /* synchronous transfer rate */ 804 #define CFSYNCH 0x0008 /* enable synchronous transfer */ 805 #define CFDISC 0x0010 /* enable disconnection */ 806 #define CFWIDEB 0x0020 /* wide bus device */ 807 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 808 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 809 #define CFSTART 0x0100 /* send start unit SCSI command */ 810 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 811 #define CFRNFOUND 0x0400 /* report even if not found */ 812 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 813 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 814 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 815 816 /* 817 * BIOS Control Bits 818 */ 819 uint16_t bios_control; /* word 16 */ 820 #define CFSUPREM 0x0001 /* support all removable drives */ 821 #define CFSUPREMB 0x0002 /* support removable boot drives */ 822 #define CFBIOSEN 0x0004 /* BIOS enabled */ 823 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 824 #define CFSM2DRV 0x0010 /* support more than two drives */ 825 #define CFSTPWLEVEL 0x0010 /* Termination level control */ 826 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 827 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 828 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 829 #define CFEXTEND 0x0080 /* extended translation enabled */ 830 #define CFSCAMEN 0x0100 /* SCAM enable */ 831 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 832 #define CFMSG_VERBOSE 0x0000 833 #define CFMSG_SILENT 0x0200 834 #define CFMSG_DIAG 0x0400 835 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 836 /* UNUSED 0xff00 */ 837 838 /* 839 * Host Adapter Control Bits 840 */ 841 uint16_t adapter_control; /* word 17 */ 842 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 843 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 844 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 845 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 846 #define CFSTERM 0x0004 /* SCSI low byte termination */ 847 #define CFWSTERM 0x0008 /* SCSI high byte termination */ 848 #define CFSPARITY 0x0010 /* SCSI parity */ 849 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 850 #define CFMULTILUN 0x0020 851 #define CFRESETB 0x0040 /* reset SCSI bus at boot */ 852 #define CFCLUSTERENB 0x0080 /* Cluster Enable */ 853 #define CFBOOTCHAN 0x0300 /* probe this channel first */ 854 #define CFBOOTCHANSHIFT 8 855 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 856 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 857 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 858 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 859 860 /* 861 * Bus Release Time, Host Adapter ID 862 */ 863 uint16_t brtime_id; /* word 18 */ 864 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 865 /* UNUSED 0x00f0 */ 866 #define CFBRTIME 0xff00 /* bus release time */ 867 868 /* 869 * Maximum targets 870 */ 871 uint16_t max_targets; /* word 19 */ 872 #define CFMAXTARG 0x00ff /* maximum targets */ 873 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 874 #define CFBOOTID 0xf000 /* Target to boot from */ 875 uint16_t res_1[10]; /* words 20-29 */ 876 uint16_t signature; /* Signature == 0x250 */ 877 #define CFSIGNATURE 0x250 878 #define CFSIGNATURE2 0x300 879 uint16_t checksum; /* word 31 */ 880 }; 881 882 /**************************** Message Buffer *********************************/ 883 typedef enum { 884 MSG_TYPE_NONE = 0x00, 885 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 886 MSG_TYPE_INITIATOR_MSGIN = 0x02, 887 MSG_TYPE_TARGET_MSGOUT = 0x03, 888 MSG_TYPE_TARGET_MSGIN = 0x04 889 } ahc_msg_type; 890 891 typedef enum { 892 MSGLOOP_IN_PROG, 893 MSGLOOP_MSGCOMPLETE, 894 MSGLOOP_TERMINATED 895 } msg_loop_stat; 896 897 /*********************** Software Configuration Structure *********************/ 898 TAILQ_HEAD(scb_tailq, scb); 899 900 struct ahc_aic7770_softc { 901 /* 902 * Saved register state used for chip_init(). 903 */ 904 uint8_t busspd; 905 uint8_t bustime; 906 }; 907 908 struct ahc_pci_softc { 909 /* 910 * Saved register state used for chip_init(). 911 */ 912 uint32_t devconfig; 913 uint16_t targcrccnt; 914 uint8_t command; 915 uint8_t csize_lattime; 916 uint8_t optionmode; 917 uint8_t crccontrol1; 918 uint8_t dscommand0; 919 uint8_t dspcistatus; 920 uint8_t scbbaddr; 921 uint8_t dff_thrsh; 922 }; 923 924 union ahc_bus_softc { 925 struct ahc_aic7770_softc aic7770_softc; 926 struct ahc_pci_softc pci_softc; 927 }; 928 929 typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 930 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 931 typedef void ahc_callback_t (void *); 932 933 struct ahc_softc { 934 struct device sc_dev; 935 936 struct scsibus_softc *sc_child; 937 struct scsibus_softc *sc_child_b; 938 939 bus_space_tag_t tag; 940 bus_space_handle_t bsh; 941 942 struct mutex sc_scb_mtx; 943 struct scsi_iopool sc_iopool; 944 945 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 946 struct scb_data *scb_data; 947 948 struct scb *next_queued_scb; 949 950 /* 951 * SCBs that have been sent to the controller 952 */ 953 LIST_HEAD(, scb) pending_scbs; 954 955 /* 956 * Counting lock for deferring the release of additional 957 * untagged transactions from the untagged_queues. When 958 * the lock is decremented to 0, all queues in the 959 * untagged_queues array are run. 960 */ 961 u_int untagged_queue_lock; 962 963 /* 964 * Per-target queue of untagged-transactions. The 965 * transaction at the head of the queue is the 966 * currently pending untagged transaction for the 967 * target. The driver only allows a single untagged 968 * transaction per target. 969 */ 970 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 971 972 /* 973 * Bus attachment specific data. 974 */ 975 union ahc_bus_softc bus_softc; 976 977 /* 978 * Platform specific device information. 979 */ 980 ahc_dev_softc_t dev_softc; 981 982 /* 983 * Bus specific device information. 984 */ 985 ahc_bus_intr_t bus_intr; 986 987 /* 988 * Bus specific initialization required 989 * after a chip reset. 990 */ 991 ahc_bus_chip_init_t bus_chip_init; 992 993 /* 994 * Target mode related state kept on a per enabled lun basis. 995 * Targets that are not enabled will have null entries. 996 * As an initiator, we keep one target entry for our initiator 997 * ID to store our sync/wide transfer settings. 998 */ 999 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 1000 1001 char inited_target[AHC_NUM_TARGETS]; 1002 1003 /* 1004 * The black hole device responsible for handling requests for 1005 * disabled luns on enabled targets. 1006 */ 1007 struct ahc_tmode_lstate *black_hole; 1008 1009 /* 1010 * Device instance currently on the bus awaiting a continue TIO 1011 * for a command that was not given the disconnect privilege. 1012 */ 1013 struct ahc_tmode_lstate *pending_device; 1014 1015 /* 1016 * Card characteristics 1017 */ 1018 ahc_chip chip; 1019 ahc_feature features; 1020 ahc_bug bugs; 1021 ahc_flag flags; 1022 struct seeprom_config *seep_config; 1023 1024 /* Values to store in the SEQCTL register for pause and unpause */ 1025 uint8_t unpause; 1026 uint8_t pause; 1027 1028 /* Command Queues */ 1029 uint8_t qoutfifonext; 1030 uint8_t qinfifonext; 1031 uint8_t *qoutfifo; 1032 uint8_t *qinfifo; 1033 1034 /* Critical Section Data */ 1035 struct cs *critical_sections; 1036 u_int num_critical_sections; 1037 1038 /* Links for chaining softcs */ 1039 TAILQ_ENTRY(ahc_softc) links; 1040 1041 /* Channel Names ('A', 'B', etc.) */ 1042 char channel; 1043 char channel_b; 1044 1045 /* Initiator Bus ID */ 1046 uint8_t our_id; 1047 uint8_t our_id_b; 1048 1049 /* 1050 * PCI error detection. 1051 */ 1052 int unsolicited_ints; 1053 1054 /* 1055 * Target incoming command FIFO. 1056 */ 1057 struct target_cmd *targetcmds; 1058 uint8_t tqinfifonext; 1059 1060 /* 1061 * Cached copy of the sequencer control register. 1062 */ 1063 uint8_t seqctl; 1064 1065 /* 1066 * Incoming and outgoing message handling. 1067 */ 1068 uint8_t send_msg_perror; 1069 ahc_msg_type msg_type; 1070 uint8_t msgout_buf[12];/* Message we are sending */ 1071 uint8_t msgin_buf[12];/* Message we are receiving */ 1072 u_int msgout_len; /* Length of message to send */ 1073 u_int msgout_index; /* Current index in msgout */ 1074 u_int msgin_index; /* Current index in msgin */ 1075 1076 /* Interrupt routine */ 1077 void *ih; 1078 1079 /* 1080 * Mapping information for data structures shared 1081 * between the sequencer and kernel. 1082 */ 1083 bus_dma_tag_t parent_dmat; 1084 bus_dmamap_t shared_data_dmamap; 1085 bus_addr_t shared_data_busaddr; 1086 1087 bus_dma_segment_t shared_data_seg; 1088 int shared_data_nseg; 1089 int shared_data_size; 1090 int sc_dmaflags; 1091 1092 /* 1093 * Bus address of the one byte buffer used to 1094 * work-around a DMA bug for chips <= aic7880 1095 * in target mode. 1096 */ 1097 bus_addr_t dma_bug_buf; 1098 1099 /* Number of enabled target mode device on this card */ 1100 u_int enabled_luns; 1101 1102 /* Initialization level of this data structure */ 1103 u_int init_level; 1104 1105 /* PCI cacheline size. */ 1106 u_int pci_cachesize; 1107 1108 /* 1109 * Count of parity errors we have seen as a target. 1110 * We auto-disable parity error checking after seeing 1111 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1112 */ 1113 u_int pci_target_perr_count; 1114 #define AHC_PCI_TARGET_PERR_THRESH 10 1115 1116 /* Maximum number of sequencer instructions supported. */ 1117 u_int instruction_ram_size; 1118 1119 /* Per-Unit descriptive information */ 1120 char *name; 1121 int unit; 1122 1123 /* Selection Timer settings */ 1124 int seltime; 1125 int seltime_b; 1126 1127 uint16_t user_discenable;/* Disconnection allowed */ 1128 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1129 1130 struct ahc_pci_busdata *bd; 1131 }; 1132 1133 TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1134 extern struct ahc_softc_tailq ahc_tailq; 1135 1136 /************************ Active Device Information ***************************/ 1137 typedef enum { 1138 ROLE_UNKNOWN, 1139 ROLE_INITIATOR, 1140 ROLE_TARGET 1141 } role_t; 1142 1143 struct ahc_devinfo { 1144 int our_scsiid; 1145 int target_offset; 1146 uint16_t target_mask; 1147 u_int target; 1148 u_int lun; 1149 char channel; 1150 role_t role; /* 1151 * Only guaranteed to be correct if not 1152 * in the busfree state. 1153 */ 1154 }; 1155 1156 /****************************** PCI Structures ********************************/ 1157 typedef int (ahc_device_setup_t)(struct ahc_softc *); 1158 1159 struct ahc_pci_identity { 1160 uint64_t full_id; 1161 uint64_t id_mask; 1162 ahc_device_setup_t *setup; 1163 }; 1164 extern const struct ahc_pci_identity ahc_pci_ident_table[]; 1165 1166 /***************************** VL/EISA Declarations ***************************/ 1167 #define AHC_EISA_SLOT_OFFSET 0xc00 1168 #define AHC_EISA_IOSIZE 0x100 1169 1170 /*************************** Function Declarations ****************************/ 1171 /******************************************************************************/ 1172 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int); 1173 void ahc_unbusy_tcl(struct ahc_softc *, u_int); 1174 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int); 1175 1176 /***************************** PCI Front End *********************************/ 1177 const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t, u_int); 1178 int ahc_pci_test_register_access(struct ahc_softc *); 1179 1180 /************************** SCB and SCB queue management **********************/ 1181 int ahc_probe_scbs(struct ahc_softc *); 1182 void ahc_run_untagged_queues(struct ahc_softc *ahc); 1183 void ahc_run_untagged_queue(struct ahc_softc *ahc, 1184 struct scb_tailq *queue); 1185 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1186 struct scb *scb); 1187 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1188 int target, char channel, int lun, 1189 u_int tag, role_t role); 1190 1191 /****************************** Initialization ********************************/ 1192 int ahc_softc_init(struct ahc_softc *); 1193 #ifndef DEBUG 1194 void ahc_controller_info(struct ahc_softc *, char *, size_t); 1195 #endif 1196 int ahc_chip_init(struct ahc_softc *ahc); 1197 int ahc_init(struct ahc_softc *ahc); 1198 void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1199 void ahc_softc_insert(struct ahc_softc *); 1200 void ahc_set_unit(struct ahc_softc *, int); 1201 void ahc_set_name(struct ahc_softc *, char *); 1202 void ahc_alloc_scbs(struct ahc_softc *ahc); 1203 void ahc_free(struct ahc_softc *ahc); 1204 int ahc_reset(struct ahc_softc *ahc, int reinit); 1205 void ahc_shutdown(void *arg); 1206 1207 /*************************** Interrupt Services *******************************/ 1208 void ahc_pci_intr(struct ahc_softc *); 1209 void ahc_clear_intstat(struct ahc_softc *); 1210 void ahc_run_qoutfifo(struct ahc_softc *); 1211 #ifdef AHC_TARGET_MODE 1212 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1213 #endif 1214 void ahc_handle_brkadrint(struct ahc_softc *ahc); 1215 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1216 void ahc_handle_scsiint(struct ahc_softc *ahc, 1217 u_int intstat); 1218 void ahc_clear_critical_section(struct ahc_softc *ahc); 1219 1220 /***************************** Error Recovery *********************************/ 1221 typedef enum { 1222 SEARCH_COMPLETE, 1223 SEARCH_COUNT, 1224 SEARCH_REMOVE 1225 } ahc_search_action; 1226 int ahc_search_qinfifo(struct ahc_softc *, int, char, 1227 int, u_int, role_t, uint32_t, ahc_search_action); 1228 int ahc_search_untagged_queues(struct ahc_softc *, 1229 struct scsi_xfer *, int, char, int, uint32_t, 1230 ahc_search_action); 1231 int ahc_search_disc_list(struct ahc_softc *, int, char, 1232 int, u_int, int, int, int); 1233 void ahc_freeze_devq(struct ahc_softc *, struct scb *); 1234 int ahc_reset_channel(struct ahc_softc *, char, int); 1235 int ahc_abort_scbs(struct ahc_softc *, int, char, int, 1236 u_int, role_t, uint32_t); 1237 void ahc_restart(struct ahc_softc *); 1238 void ahc_calc_residual(struct ahc_softc *, struct scb *); 1239 /*************************** Utility Functions ********************************/ 1240 struct ahc_phase_table_entry* 1241 ahc_lookup_phase_entry(int phase); 1242 void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1243 u_int our_id, u_int target, 1244 u_int lun, char channel, 1245 role_t role); 1246 /************************** Transfer Negotiation ******************************/ 1247 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1248 u_int *ppr_options, u_int maxsync); 1249 u_int ahc_find_period(struct ahc_softc *ahc, 1250 u_int scsirate, u_int maxsync); 1251 void ahc_validate_offset(struct ahc_softc *ahc, 1252 struct ahc_initiator_tinfo *tinfo, 1253 struct ahc_syncrate *syncrate, 1254 u_int *offset, int wide, 1255 role_t role); 1256 void ahc_validate_width(struct ahc_softc *ahc, 1257 struct ahc_initiator_tinfo *tinfo, 1258 u_int *bus_width, 1259 role_t role); 1260 /* 1261 * Negotiation types. These are used to qualify if we should renegotiate 1262 * even if our goal and current transport parameters are identical. 1263 */ 1264 typedef enum { 1265 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1266 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1267 AHC_NEG_ALWAYS /* Renegotiate even if goal is async. */ 1268 } ahc_neg_type; 1269 int ahc_update_neg_request(struct ahc_softc *, 1270 struct ahc_devinfo *, struct ahc_tmode_tstate *, 1271 struct ahc_initiator_tinfo*, ahc_neg_type); 1272 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *, 1273 u_int, u_int, int); 1274 void ahc_set_syncrate(struct ahc_softc *, 1275 struct ahc_devinfo *, struct ahc_syncrate *, 1276 u_int, u_int, u_int, u_int, int); 1277 void ahc_scb_devinfo(struct ahc_softc *, 1278 struct ahc_devinfo *, struct scb *); 1279 1280 1281 typedef enum { 1282 AHC_QUEUE_NONE, 1283 AHC_QUEUE_BASIC, 1284 AHC_QUEUE_TAGGED 1285 } ahc_queue_alg; 1286 1287 void ahc_set_tags(struct ahc_softc *ahc, 1288 struct ahc_devinfo *devinfo, 1289 ahc_queue_alg alg); 1290 1291 /**************************** Target Mode *************************************/ 1292 #ifdef AHC_TARGET_MODE 1293 void ahc_send_lstate_events(struct ahc_softc *, 1294 struct ahc_tmode_lstate *); 1295 void ahc_handle_en_lun(struct ahc_softc *, struct scsi_xfer *); 1296 cam_status ahc_find_tmode_devs(struct ahc_softc *, 1297 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **, 1298 int); 1299 #ifndef AHC_TMODE_ENABLE 1300 #define AHC_TMODE_ENABLE 0 1301 #endif 1302 #endif 1303 /******************************* Debug ***************************************/ 1304 #ifdef AHC_DEBUG 1305 extern uint32_t ahc_debug; 1306 #define AHC_SHOW_MISC 0x0001 1307 #define AHC_SHOW_SENSE 0x0002 1308 #define AHC_DUMP_SEEPROM 0x0004 1309 #define AHC_SHOW_TERMCTL 0x0008 1310 #define AHC_SHOW_MEMORY 0x0010 1311 #define AHC_SHOW_MESSAGES 0x0020 1312 #define AHC_SHOW_DV 0x0040 1313 #define AHC_SHOW_SELTO 0x0080 1314 #define AHC_SHOW_QFULL 0x0200 1315 #define AHC_SHOW_QUEUE 0x0400 1316 #define AHC_SHOW_TQIN 0x0800 1317 #define AHC_SHOW_MASKED_ERRORS 0x1000 1318 #define AHC_DEBUG_SEQUENCER 0x2000 1319 #endif 1320 void ahc_print_scb(struct scb *scb); 1321 void ahc_print_devinfo(struct ahc_softc *ahc, 1322 struct ahc_devinfo *dev); 1323 void ahc_dump_card_state(struct ahc_softc *ahc); 1324 int ahc_print_register(ahc_reg_parse_entry_t *table, 1325 u_int num_entries, 1326 const char *name, 1327 u_int address, 1328 u_int value, 1329 u_int *cur_column, 1330 u_int wrap_point); 1331 /******************************* SEEPROM *************************************/ 1332 int ahc_acquire_seeprom(struct ahc_softc *ahc, 1333 struct seeprom_descriptor *sd); 1334 void ahc_release_seeprom(struct seeprom_descriptor *sd); 1335 1336 void ahc_check_extport(struct ahc_softc *, u_int *); 1337 #endif /* _AIC7XXXVAR_H_ */ 1338