1 /* $OpenBSD: aic79xx.h,v 1.34 2024/10/22 21:50:02 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Core definitions and data structures shareable across OS platforms. 32 * 33 * Copyright (c) 1994-2002 Justin T. Gibbs. 34 * Copyright (c) 2000-2002 Adaptec Inc. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions, and the following disclaimer, 42 * without modification. 43 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 44 * substantially similar to the "NO WARRANTY" disclaimer below 45 * ("Disclaimer") and any redistribution must be conditioned upon 46 * including a substantially similar Disclaimer requirement for further 47 * binary redistribution. 48 * 3. Neither the names of the above-listed copyright holders nor the names 49 * of any contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * Alternatively, this software may be distributed under the terms of the 53 * GNU General Public License ("GPL") version 2 as published by the Free 54 * Software Foundation. 55 * 56 * NO WARRANTY 57 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 58 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 60 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 61 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 65 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 66 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGES. 68 * 69 * Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 70 * 71 * FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.23 2004/11/18 20:22:31 gibbs Exp 72 */ 73 74 #ifndef _AIC79XX_H_ 75 #define _AIC79XX_H_ 76 77 /* #define AHD_DEBUG */ 78 79 /* Register Definitions */ 80 #include <dev/microcode/aic7xxx/aic79xx_reg.h> 81 82 #include <dev/ic/aic7xxx_cam.h> 83 84 /****************************** Useful Macros *********************************/ 85 #ifndef MAX 86 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 87 #endif 88 89 #ifndef MIN 90 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 91 #endif 92 93 #ifndef TRUE 94 #define TRUE 1 95 #endif 96 #ifndef FALSE 97 #define FALSE 0 98 #endif 99 100 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 101 102 #define ALL_CHANNELS '\0' 103 #define ALL_TARGETS_MASK 0xFFFF 104 #define INITIATOR_WILDCARD (~0) 105 #define SCB_LIST_NULL 0xFF00 106 #define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 107 #define QOUTFIFO_ENTRY_VALID 0x80 108 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 109 110 #define SCSIID_TARGET(ahd, scsiid) \ 111 (((scsiid) & TID) >> TID_SHIFT) 112 #define SCSIID_OUR_ID(scsiid) \ 113 ((scsiid) & OID) 114 #define SCSIID_CHANNEL(ahd, scsiid) ('A') 115 #define SCB_IS_SCSIBUS_B(ahd, scb) (0) 116 #define SCB_GET_OUR_ID(scb) \ 117 SCSIID_OUR_ID((scb)->hscb->scsiid) 118 #define SCB_GET_TARGET(ahd, scb) \ 119 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 120 #define SCB_GET_CHANNEL(ahd, scb) \ 121 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 122 #define SCB_GET_LUN(scb) \ 123 ((scb)->hscb->lun) 124 #define SCB_GET_TARGET_OFFSET(ahd, scb) \ 125 SCB_GET_TARGET(ahd, scb) 126 #define SCB_GET_TARGET_MASK(ahd, scb) \ 127 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 128 #ifdef AHD_DEBUG 129 #define SCB_IS_SILENT(scb) \ 130 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 131 && (((scb)->flags & SCB_SILENT) != 0)) 132 #else 133 #define SCB_IS_SILENT(scb) \ 134 (((scb)->flags & SCB_SILENT) != 0) 135 #endif 136 /* 137 * TCLs have the following format: TTTTLLLLLLLL 138 */ 139 #define TCL_TARGET_OFFSET(tcl) \ 140 ((((tcl) >> 4) & TID) >> 4) 141 #define TCL_LUN(tcl) \ 142 (tcl & (AHD_NUM_LUNS - 1)) 143 #define BUILD_TCL(scsiid, lun) \ 144 ((lun) | (((scsiid) & TID) << 4)) 145 #define BUILD_TCL_RAW(target, channel, lun) \ 146 ((lun) | ((target) << 8)) 147 148 #define SCB_GET_TAG(scb) \ 149 aic_le16toh(scb->hscb->tag) 150 151 #ifndef AHD_TARGET_MODE 152 #undef AHD_TMODE_ENABLE 153 #define AHD_TMODE_ENABLE 0 154 #endif 155 156 /**************************** Driver Constants ********************************/ 157 /* 158 * The maximum number of supported targets. 159 */ 160 #define AHD_NUM_TARGETS 16 161 162 /* 163 * The maximum number of supported luns. 164 * The identify message only supports 64 luns in non-packetized transfers. 165 * You can have 2^64 luns when information unit transfers are enabled, 166 * but until we see a need to support that many, we support 256. 167 */ 168 #define AHD_NUM_LUNS_NONPKT 64 169 #define AHD_NUM_LUNS 256 170 171 /* 172 * The maximum transfer per S/G segment. 173 */ 174 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 175 176 /* 177 * The maximum amount of SCB storage in hardware on a controller. 178 * This value represents an upper bound. Due to software design, 179 * we may not be able to use this number. 180 */ 181 #define AHD_SCB_MAX 512 182 183 /* 184 * The maximum number of concurrent transactions supported per driver instance. 185 * Sequencer Control Blocks (SCBs) store per-transaction information. 186 */ 187 #define AHD_MAX_QUEUE AHD_SCB_MAX 188 189 /* 190 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 191 * in size and accommodate as many transactions as can be queued concurrently. 192 */ 193 #define AHD_QIN_SIZE AHD_MAX_QUEUE 194 #define AHD_QOUT_SIZE AHD_MAX_QUEUE 195 196 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 197 /* 198 * The maximum amount of SCB storage we allocate in host memory. 199 */ 200 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 201 202 /* 203 * Ring Buffer of incoming target commands. 204 * We allocate 256 to simplify the logic in the sequencer 205 * by using the natural wrap point of an 8bit counter. 206 */ 207 #define AHD_TMODE_CMDS 256 208 209 /* Reset line assertion time in us */ 210 #define AHD_BUSRESET_DELAY 25 211 212 /******************* Chip Characteristics/Operating Settings *****************/ 213 extern uint32_t ahd_attach_to_HostRAID_controllers; 214 215 /* 216 * Chip Type 217 * The chip order is from least sophisticated to most sophisticated. 218 */ 219 typedef enum { 220 AHD_NONE = 0x0000, 221 AHD_CHIPID_MASK = 0x00FF, 222 AHD_AIC7901 = 0x0001, 223 AHD_AIC7902 = 0x0002, 224 AHD_AIC7901A = 0x0003, 225 AHD_PCI = 0x0100, /* Bus type PCI */ 226 AHD_PCIX = 0x0200, /* Bus type PCIX */ 227 AHD_BUS_MASK = 0x0F00 228 } ahd_chip; 229 230 /* 231 * Features available in each chip type. 232 */ 233 typedef enum { 234 AHD_FENONE = 0x00000, 235 AHD_WIDE = 0x00001,/* Wide Channel */ 236 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 237 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 238 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 239 AHD_RTI = 0x04000,/* Retained Training Support */ 240 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 241 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 242 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 243 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 244 AHD_AIC7901_FE = AHD_FENONE, 245 AHD_AIC7901A_FE = AHD_FENONE, 246 AHD_AIC7902_FE = AHD_MULTI_FUNC 247 } ahd_feature; 248 249 /* 250 * Bugs in the silicon that we work around in software. 251 */ 252 typedef enum { 253 AHD_BUGNONE = 0x0000, 254 /* 255 * Rev A hardware fails to update LAST/CURR/NEXTSCB 256 * correctly in certain packetized selection cases. 257 */ 258 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 259 /* The wrong SCB is accessed to check the abort pending bit. */ 260 AHD_ABORT_LQI_BUG = 0x0002, 261 /* Packetized bitbucket crosses packet boundaries. */ 262 AHD_PKT_BITBUCKET_BUG = 0x0004, 263 /* The selection timer runs twice as long as its setting. */ 264 AHD_LONG_SETIMO_BUG = 0x0008, 265 /* The Non-LQ CRC error status is delayed until phase change. */ 266 AHD_NLQICRC_DELAYED_BUG = 0x0010, 267 /* The chip must be reset for all outgoing bus resets. */ 268 AHD_SCSIRST_BUG = 0x0020, 269 /* Some PCIX fields must be saved and restored across chip reset. */ 270 AHD_PCIX_CHIPRST_BUG = 0x0040, 271 /* MMAPIO is not functional in PCI-X mode. */ 272 AHD_PCIX_MMAPIO_BUG = 0x0080, 273 /* Reads to SCBRAM fail to reset the discard timer. */ 274 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 275 /* Bug workarounds that can be disabled on non-PCIX busses. */ 276 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 277 | AHD_PCIX_MMAPIO_BUG 278 | AHD_PCIX_SCBRAM_RD_BUG, 279 /* 280 * LQOSTOP0 status set even for forced selections with ATN 281 * to perform non-packetized message delivery. 282 */ 283 AHD_LQO_ATNO_BUG = 0x0200, 284 /* FIFO auto-flush does not always trigger. */ 285 AHD_AUTOFLUSH_BUG = 0x0400, 286 /* The CLRLQO registers are not self-clearing. */ 287 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 288 /* The PACKETIZED status bit refers to the previous connection. */ 289 AHD_PKTIZED_STATUS_BUG = 0x1000, 290 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 291 AHD_PKT_LUN_BUG = 0x2000, 292 /* 293 * Only the FIFO allocated to the non-packetized connection may 294 * be in use during a non-packetzied connection. 295 */ 296 AHD_NONPACKFIFO_BUG = 0x4000, 297 /* 298 * Writing to a DFF SCBPTR register may fail if concurrent with 299 * a hardware write to the other DFF SCBPTR register. This is 300 * not currently a concern in our sequencer since all chips with 301 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 302 * occur in non-packetized connections. 303 */ 304 AHD_MDFF_WSCBPTR_BUG = 0x8000, 305 /* SGHADDR updates are slow. */ 306 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 307 /* 308 * Changing the MODE_PTR coincident with an interrupt that 309 * switches to a different mode will cause the interrupt to 310 * be in the mode written outside of interrupt context. 311 */ 312 AHD_SET_MODE_BUG = 0x20000, 313 /* Non-packetized busfree revision does not work. */ 314 AHD_BUSFREEREV_BUG = 0x40000, 315 /* 316 * Paced transfers are indicated with a non-standard PPR 317 * option bit in the neg table, 160MHz is indicated by 318 * sync factor 0x7, and the offset if off by a factor of 2. 319 */ 320 AHD_PACED_NEGTABLE_BUG = 0x80000, 321 /* LQOOVERRUN false positives. */ 322 AHD_LQOOVERRUN_BUG = 0x100000, 323 /* 324 * Controller write to INTSTAT will lose to a host 325 * write to CLRINT. 326 */ 327 AHD_INTCOLLISION_BUG = 0x200000, 328 /* 329 * The GEM318 violates the SCSI spec by not waiting 330 * the mandated bus settle delay between phase changes 331 * in some situations. Some aic79xx chip revs. are more 332 * strict in this regard and will treat REQ assertions 333 * that fall within the bus settle delay window as 334 * glitches. This flag tells the firmware to tolerate 335 * early REQ assertions. 336 */ 337 AHD_EARLY_REQ_BUG = 0x400000, 338 /* 339 * The LED does not stay on long enough in packetized modes. 340 */ 341 AHD_FAINT_LED_BUG = 0x800000 342 } ahd_bug; 343 344 /* 345 * Configuration specific settings. 346 * The driver determines these settings by probing the 347 * chip/controller's configuration. 348 */ 349 typedef enum { 350 AHD_FNONE = 0x00000, 351 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 352 AHD_USEDEFAULTS = 0x00004,/* 353 * For cards without an seeprom 354 * or a BIOS to initialize the chip's 355 * SRAM, we use the default target 356 * settings. 357 */ 358 AHD_SEQUENCER_DEBUG = 0x00008, 359 AHD_RESET_BUS_A = 0x00010, 360 AHD_EXTENDED_TRANS_A = 0x00020, 361 AHD_TERM_ENB_A = 0x00040, 362 AHD_SPCHK_ENB_A = 0x00080, 363 AHD_STPWLEVEL_A = 0x00100, 364 AHD_INITIATORROLE = 0x00200,/* 365 * Allow initiator operations on 366 * this controller. 367 */ 368 AHD_TARGETROLE = 0x00400,/* 369 * Allow target operations on this 370 * controller. 371 */ 372 AHD_RESOURCE_SHORTAGE = 0x00800, 373 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 374 AHD_INT50_SPEEDFLEX = 0x02000,/* 375 * Internal 50pin connector 376 * sits behind an aic3860 377 */ 378 AHD_BIOS_ENABLED = 0x04000, 379 AHD_ALL_INTERRUPTS = 0x08000, 380 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 381 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 382 AHD_CURRENT_SENSING = 0x40000, 383 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 384 AHD_HP_BOARD = 0x100000, 385 AHD_RESET_POLL_ACTIVE = 0x200000, 386 AHD_UPDATE_PEND_CMDS = 0x400000, 387 AHD_RUNNING_QOUTFIFO = 0x800000, 388 AHD_HAD_FIRST_SEL = 0x1000000, 389 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */ 390 AHD_HOSTRAID_BOARD = 0x4000000 391 } ahd_flag; 392 393 /************************* Hardware SCB Definition ***************************/ 394 395 /* 396 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 397 * consists of a "hardware SCB" mirroring the fields available on the card 398 * and additional information the kernel stores for each transaction. 399 * 400 * To minimize space utilization, a portion of the hardware scb stores 401 * different data during different portions of a SCSI transaction. 402 * As initialized by the host driver for the initiator role, this area 403 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 404 * the cdb has been presented to the target, this area serves to store 405 * residual transfer information and the SCSI status byte. 406 * For the target role, the contents of this area do not change, but 407 * still serve a different purpose than for the initiator role. See 408 * struct target_data for details. 409 */ 410 411 /* 412 * Status information embedded in the shared portion of 413 * an SCB after passing the cdb to the target. The kernel 414 * driver will only read this data for transactions that 415 * complete abnormally. 416 */ 417 struct initiator_status { 418 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 419 uint32_t residual_sgptr; /* The next S/G for this transfer */ 420 uint8_t scsi_status; /* Standard SCSI status byte */ 421 }; 422 423 struct target_status { 424 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 425 uint32_t residual_sgptr; /* The next S/G for this transfer */ 426 uint8_t scsi_status; /* SCSI status to give to initiator */ 427 uint8_t target_phases; /* Bitmap of phases to execute */ 428 uint8_t data_phase; /* Data-In or Data-Out */ 429 uint8_t initiator_tag; /* Initiator's transaction tag */ 430 }; 431 432 /* 433 * Initiator mode SCB shared data area. 434 * If the embedded CDB is 12 bytes or less, we embed 435 * the sense buffer address in the SCB. This allows 436 * us to retrieve sense information without interrupting 437 * the host in packetized mode. 438 */ 439 typedef uint32_t sense_addr_t; 440 #define MAX_CDB_LEN 16 441 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 442 union initiator_data { 443 struct { 444 uint64_t cdbptr; 445 uint8_t cdblen; 446 } cdb_from_host; 447 uint8_t cdb[MAX_CDB_LEN]; 448 struct { 449 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 450 sense_addr_t sense_addr; 451 } cdb_plus_saddr; 452 }; 453 454 /* 455 * Target mode version of the shared data SCB segment. 456 */ 457 struct target_data { 458 uint32_t spare[2]; 459 uint8_t scsi_status; /* SCSI status to give to initiator */ 460 uint8_t target_phases; /* Bitmap of phases to execute */ 461 uint8_t data_phase; /* Data-In or Data-Out */ 462 uint8_t initiator_tag; /* Initiator's transaction tag */ 463 }; 464 465 struct hardware_scb { 466 /*0*/ union { 467 union initiator_data idata; 468 struct target_data tdata; 469 struct initiator_status istatus; 470 struct target_status tstatus; 471 } shared_data; 472 /* 473 * A word about residuals. 474 * The scb is presented to the sequencer with the dataptr and datacnt 475 * fields initialized to the contents of the first S/G element to 476 * transfer. The sgptr field is initialized to the bus address for 477 * the S/G element that follows the first in the in core S/G array 478 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 479 * S/G entry for this transfer (single S/G element transfer with the 480 * first elements address and length preloaded in the dataptr/datacnt 481 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 482 * The SG_FULL_RESID flag ensures that the residual will be correctly 483 * noted even if no data transfers occur. Once the data phase is entered, 484 * the residual sgptr and datacnt are loaded from the sgptr and the 485 * datacnt fields. After each S/G element's dataptr and length are 486 * loaded into the hardware, the residual sgptr is advanced. After 487 * each S/G element is expired, its datacnt field is checked to see 488 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 489 * residual sg ptr and the transfer is considered complete. If the 490 * sequencer determines that there is a residual in the transfer, or 491 * there is non-zero status, it will set the SG_STATUS_VALID flag in 492 * sgptr and dma the scb back into host memory. To summarize: 493 * 494 * Sequencer: 495 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 496 * or residual_sgptr does not have SG_LIST_NULL set. 497 * 498 * o We are transferring the last segment if residual_datacnt has 499 * the SG_LAST_SEG flag set. 500 * 501 * Host: 502 * o A residual can only have occurred if a completed scb has the 503 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 504 * the residual_datacnt, and the residual_sgptr field will tell 505 * for sure. 506 * 507 * o residual_sgptr and sgptr refer to the "next" sg entry 508 * and so may point beyond the last valid sg entry for the 509 * transfer. 510 */ 511 #define SG_PTR_MASK 0xFFFFFFF8 512 /*16*/ uint16_t tag; /* Reused by Sequencer. */ 513 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 514 /*19*/ uint8_t scsiid; /* 515 * Selection out Id 516 * Our Id (bits 0-3) Their ID (bits 4-7) 517 */ 518 /*20*/ uint8_t lun; 519 /*21*/ uint8_t task_attribute; 520 /*22*/ uint8_t cdb_len; 521 /*23*/ uint8_t task_management; 522 /*24*/ uint64_t dataptr; 523 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 524 /*36*/ uint32_t sgptr; 525 /*40*/ uint32_t hscb_busaddr; 526 /*44*/ uint32_t next_hscb_busaddr; 527 /********** Long lun field only downloaded for full 8 byte lun support ********/ 528 /*48*/ uint8_t pkt_long_lun[8]; 529 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 530 /*56*/ uint8_t spare[8]; 531 }; 532 533 /************************ Kernel SCB Definitions ******************************/ 534 /* 535 * Some fields of the SCB are OS dependent. Here we collect the 536 * definitions for elements that all OS platforms need to include 537 * in there SCB definition. 538 */ 539 540 /* 541 * Definition of a scatter/gather element as transferred to the controller. 542 * The aic7xxx chips only support a 24bit length. We use the top byte of 543 * the length to store additional address bits and a flag to indicate 544 * that a given segment terminates the transfer. This gives us an 545 * addressable range of 512GB on machines with 64bit PCI or with chips 546 * that can support dual address cycles on 32bit PCI busses. 547 */ 548 struct ahd_dma_seg { 549 uint32_t addr; 550 uint32_t len; 551 #define AHD_DMA_LAST_SEG 0x80000000 552 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000 553 #define AHD_SG_LEN_MASK 0x00FFFFFF 554 }; 555 556 struct ahd_dma64_seg { 557 uint64_t addr; 558 uint32_t len; 559 uint32_t pad; 560 }; 561 562 struct map_node { 563 bus_dmamap_t dmamap; 564 bus_addr_t busaddr; 565 uint8_t *vaddr; 566 bus_dma_segment_t dmaseg; 567 size_t size; 568 SLIST_ENTRY(map_node) links; 569 }; 570 571 /* 572 * The current state of this SCB. 573 */ 574 typedef enum { 575 SCB_FLAG_NONE = 0x00000, 576 SCB_TRANSMISSION_ERROR = 0x00001,/* 577 * We detected a parity or CRC 578 * error that has effected the 579 * payload of the command. This 580 * flag is checked when normal 581 * status is returned to catch 582 * the case of a target not 583 * responding to our attempt 584 * to report the error. 585 */ 586 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 587 * Another device was active 588 * during the first timeout for 589 * this SCB so we gave ourselves 590 * an additional timeout period 591 * in case it was hogging the 592 * bus. 593 */ 594 SCB_DEVICE_RESET = 0x00004, 595 SCB_SENSE = 0x00008, 596 SCB_CDB32_PTR = 0x00010, 597 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 598 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 599 SCB_ABORT = 0x00100, 600 SCB_ACTIVE = 0x00200, 601 SCB_TARGET_IMMEDIATE = 0x00400, 602 SCB_PACKETIZED = 0x00800, 603 SCB_EXPECT_PPR_BUSFREE = 0x01000, 604 SCB_PKT_SENSE = 0x02000, 605 SCB_CMDPHASE_ABORT = 0x04000, 606 SCB_ON_COL_LIST = 0x08000, 607 SCB_SILENT = 0x10000,/* 608 * Be quiet about transmission type 609 * errors. They are expected and we 610 * don't want to upset the user. This 611 * flag is typically used during DV. 612 */ 613 } scb_flag; 614 615 struct scb { 616 TAILQ_ENTRY(scb) next; 617 struct hardware_scb *hscb; 618 LIST_ENTRY(scb) timedout_links; 619 struct scsi_xfer *xs; 620 621 struct ahd_softc *ahd_softc; 622 scb_flag flags; 623 bus_dmamap_t dmamap; 624 struct map_node *hscb_map; 625 struct map_node *sg_map; 626 struct map_node *sense_map; 627 void *sg_list; 628 uint8_t *sense_data; 629 bus_addr_t sg_list_busaddr; 630 bus_addr_t sense_busaddr; 631 u_int sg_count;/* How full ahd_dma_seg is */ 632 #define AHD_MAX_LQ_CRC_ERRORS 5 633 u_int crc_retry_count; 634 }; 635 636 TAILQ_HEAD(scb_tailq, scb); 637 LIST_HEAD(scb_list, scb); 638 639 struct scb_data { 640 /* 641 * SCBs that will not collide with any active device. 642 */ 643 struct scb_tailq free_scbs; 644 645 /* 646 * Mapping from tag to SCB. 647 */ 648 struct scb *scbindex[AHD_SCB_MAX]; 649 650 u_int recovery_scbs; /* Transactions currently in recovery */ 651 652 SLIST_HEAD(, map_node) hscb_maps; 653 SLIST_HEAD(, map_node) sg_maps; 654 SLIST_HEAD(, map_node) sense_maps; 655 int scbs_left; /* unallocated scbs in head map_node */ 656 int sgs_left; /* unallocated sgs in head map_node */ 657 int sense_left; /* unallocated sense in head map_node */ 658 uint16_t numscbs; 659 uint16_t maxhscbs; /* Number of SCBs on the card */ 660 uint8_t init_level; /* 661 * How far we've initialized 662 * this structure. 663 */ 664 }; 665 666 /************************ Target Mode Definitions *****************************/ 667 668 /* 669 * Connection descriptor for select-in requests in target mode. 670 */ 671 struct target_cmd { 672 uint8_t scsiid; /* Our ID and the initiator's ID */ 673 uint8_t identify; /* Identify message */ 674 uint8_t bytes[22]; /* 675 * Bytes contains any additional message 676 * bytes terminated by 0xFF. The remainder 677 * is the cdb to execute. 678 */ 679 uint8_t cmd_valid; /* 680 * When a command is complete, the firmware 681 * will set cmd_valid to all bits set. 682 * After the host has seen the command, 683 * the bits are cleared. This allows us 684 * to just peek at host memory to determine 685 * if more work is complete. cmd_valid is on 686 * an 8 byte boundary to simplify setting 687 * it on aic7880 hardware which only has 688 * limited direct access to the DMA FIFO. 689 */ 690 uint8_t pad[7]; 691 }; 692 693 /* 694 * Number of events we can buffer up if we run out 695 * of immediate notify ccbs. 696 */ 697 #define AHD_TMODE_EVENT_BUFFER_SIZE 8 698 struct ahd_tmode_event { 699 uint8_t initiator_id; 700 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 701 #define EVENT_TYPE_BUS_RESET 0xFF 702 uint8_t event_arg; 703 }; 704 705 /* 706 * Per enabled lun target mode state. 707 * As this state is directly influenced by the host OS'es target mode 708 * environment, we let the OS module define it. Forward declare the 709 * structure here so we can store arrays of them, etc. in OS neutral 710 * data structures. 711 */ 712 #ifdef AHD_TARGET_MODE 713 struct ahd_tmode_lstate { 714 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 715 uint8_t event_r_idx; 716 uint8_t event_w_idx; 717 }; 718 #else 719 struct ahd_tmode_lstate; 720 #endif 721 722 /******************** Transfer Negotiation Datastructures *********************/ 723 #define AHD_TRANS_CUR 0x01 /* Modify current negotiation status */ 724 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 725 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 726 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 727 #define AHD_PERIOD_10MHz 0x19 728 729 #define AHD_WIDTH_UNKNOWN 0xFF 730 #define AHD_PERIOD_UNKNOWN 0xFF 731 #define AHD_OFFSET_UNKNOWN 0xFF 732 #define AHD_PPR_OPTS_UNKNOWN 0xFF 733 734 /* 735 * Transfer Negotiation Information. 736 */ 737 struct ahd_transinfo { 738 uint8_t protocol_version; /* SCSI Revision level */ 739 uint8_t transport_version; /* SPI Revision level */ 740 uint8_t width; /* Bus width */ 741 uint8_t period; /* Sync rate factor */ 742 uint8_t offset; /* Sync offset */ 743 uint8_t ppr_options; /* Parallel Protocol Request options */ 744 }; 745 746 /* 747 * Per-initiator current, goal and user transfer negotiation information. */ 748 struct ahd_initiator_tinfo { 749 struct ahd_transinfo curr; 750 struct ahd_transinfo goal; 751 struct ahd_transinfo user; 752 }; 753 754 /* 755 * Per enabled target ID state. 756 * Pointers to lun target state as well as sync/wide negotiation information 757 * for each initiator<->target mapping. For the initiator role we pretend 758 * that we are the target and the targets are the initiators since the 759 * negotiation is the same regardless of role. 760 */ 761 struct ahd_tmode_tstate { 762 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 763 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 764 765 /* 766 * Per initiator state bitmasks. 767 */ 768 uint16_t auto_negotiate;/* Auto Negotiation Required */ 769 uint16_t discenable; /* Disconnection allowed */ 770 uint16_t tagenable; /* Tagged Queuing allowed */ 771 }; 772 773 /* 774 * Points of interest along the negotiated transfer scale. 775 */ 776 #define AHD_SYNCRATE_160 0x8 777 #define AHD_SYNCRATE_PACED 0x8 778 #define AHD_SYNCRATE_DT 0x9 779 #define AHD_SYNCRATE_ULTRA2 0xa 780 #define AHD_SYNCRATE_ULTRA 0xc 781 #define AHD_SYNCRATE_FAST 0x19 782 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 783 #define AHD_SYNCRATE_SYNC 0x32 784 #define AHD_SYNCRATE_MIN 0x60 785 #define AHD_SYNCRATE_ASYNC 0xFF 786 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 787 788 /* Safe and valid period for async negotiations. */ 789 #define AHD_ASYNC_XFER_PERIOD 0x44 790 791 /* 792 * In RevA, the synctable uses a 120MHz rate for the period 793 * factor 8 and 160MHz for the period factor 7. The 120MHz 794 * rate never made it into the official SCSI spec, so we must 795 * compensate when setting the negotiation table for Rev A 796 * parts. 797 */ 798 #define AHD_SYNCRATE_REVA_120 0x8 799 #define AHD_SYNCRATE_REVA_160 0x7 800 801 /***************************** Lookup Tables **********************************/ 802 /* 803 * Phase -> name and message out response 804 * to parity errors in each phase table. 805 */ 806 struct ahd_phase_table_entry { 807 uint8_t phase; 808 uint8_t mesg_out; /* Message response to parity errors */ 809 char *phasemsg; 810 }; 811 812 /************************** Serial EEPROM Format ******************************/ 813 814 struct seeprom_config { 815 /* 816 * Per SCSI ID Configuration Flags 817 */ 818 uint16_t device_flags[16]; /* words 0-15 */ 819 #define CFXFER 0x003F /* synchronous transfer rate */ 820 #define CFXFER_ASYNC 0x3F 821 #define CFQAS 0x0040 /* Negotiate QAS */ 822 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 823 #define CFSTART 0x0100 /* send start unit SCSI command */ 824 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 825 #define CFDISC 0x0400 /* enable disconnection */ 826 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 827 #define CFWIDEB 0x1000 /* wide bus device */ 828 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 829 830 /* 831 * BIOS Control Bits 832 */ 833 uint16_t bios_control; /* word 16 */ 834 #define CFSUPREM 0x0001 /* support all removable drives */ 835 #define CFSUPREMB 0x0002 /* support removable boot drives */ 836 #define CFBIOSSTATE 0x000C /* BIOS Action State */ 837 #define CFBS_DISABLED 0x00 838 #define CFBS_ENABLED 0x04 839 #define CFBS_DISABLED_SCAN 0x08 840 #define CFENABLEDV 0x0010 /* Perform Domain Validation */ 841 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 842 #define CFSPARITY 0x0040 /* SCSI parity */ 843 #define CFEXTEND 0x0080 /* extended translation enabled */ 844 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 845 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 846 #define CFMSG_VERBOSE 0x0000 847 #define CFMSG_SILENT 0x0200 848 #define CFMSG_DIAG 0x0400 849 #define CFRESETB 0x0800 /* reset SCSI bus at boot */ 850 /* UNUSED 0xf000 */ 851 852 /* 853 * Host Adapter Control Bits 854 */ 855 uint16_t adapter_control; /* word 17 */ 856 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 857 #define CFSTERM 0x0002 /* SCSI low byte termination */ 858 #define CFWSTERM 0x0004 /* SCSI high byte termination */ 859 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 860 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 861 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 862 #define CFSTPWLEVEL 0x0040 /* Termination level control */ 863 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 864 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 865 #define CFCLUSTERENB 0x8000 /* Cluster Enable */ 866 867 /* 868 * Bus Release Time, Host Adapter ID 869 */ 870 uint16_t brtime_id; /* word 18 */ 871 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 872 /* UNUSED 0x00f0 */ 873 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 874 875 /* 876 * Maximum targets 877 */ 878 uint16_t max_targets; /* word 19 */ 879 #define CFMAXTARG 0x00ff /* maximum targets */ 880 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 881 #define CFBOOTID 0xf000 /* Target to boot from */ 882 uint16_t res_1[10]; /* words 20-29 */ 883 uint16_t signature; /* BIOS Signature */ 884 #define CFSIGNATURE 0x400 885 uint16_t checksum; /* word 31 */ 886 }; 887 888 /* 889 * Vital Product Data used during POST and by the BIOS. 890 */ 891 struct vpd_config { 892 uint8_t bios_flags; 893 #define VPDMASTERBIOS 0x0001 894 #define VPDBOOTHOST 0x0002 895 uint8_t reserved_1[21]; 896 uint8_t resource_type; 897 uint8_t resource_len[2]; 898 uint8_t resource_data[8]; 899 uint8_t vpd_tag; 900 uint16_t vpd_len; 901 uint8_t vpd_keyword[2]; 902 uint8_t length; 903 uint8_t revision; 904 uint8_t device_flags; 905 uint8_t termnation_menus[2]; 906 uint8_t fifo_threshold; 907 uint8_t end_tag; 908 uint8_t vpd_checksum; 909 uint16_t default_target_flags; 910 uint16_t default_bios_flags; 911 uint16_t default_ctrl_flags; 912 uint8_t default_irq; 913 uint8_t pci_lattime; 914 uint8_t max_target; 915 uint8_t boot_lun; 916 uint16_t signature; 917 uint8_t reserved_2; 918 uint8_t checksum; 919 uint8_t reserved_3[4]; 920 }; 921 922 /****************************** Flexport Logic ********************************/ 923 #define FLXADDR_TERMCTL 0x0 924 #define FLX_TERMCTL_ENSECHIGH 0x8 925 #define FLX_TERMCTL_ENSECLOW 0x4 926 #define FLX_TERMCTL_ENPRIHIGH 0x2 927 #define FLX_TERMCTL_ENPRILOW 0x1 928 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1 929 #define FLX_ROMSTAT_SEECFG 0xF0 930 #define FLX_ROMSTAT_EECFG 0x0F 931 #define FLX_ROMSTAT_SEE_93C66 0x00 932 #define FLX_ROMSTAT_SEE_NONE 0xF0 933 #define FLX_ROMSTAT_EE_512x8 0x0 934 #define FLX_ROMSTAT_EE_1MBx8 0x1 935 #define FLX_ROMSTAT_EE_2MBx8 0x2 936 #define FLX_ROMSTAT_EE_4MBx8 0x3 937 #define FLX_ROMSTAT_EE_16MBx8 0x4 938 #define CURSENSE_ENB 0x1 939 #define FLXADDR_FLEXSTAT 0x2 940 #define FLX_FSTAT_BUSY 0x1 941 #define FLXADDR_CURRENT_STAT 0x4 942 #define FLX_CSTAT_SEC_HIGH 0xC0 943 #define FLX_CSTAT_SEC_LOW 0x30 944 #define FLX_CSTAT_PRI_HIGH 0x0C 945 #define FLX_CSTAT_PRI_LOW 0x03 946 #define FLX_CSTAT_MASK 0x03 947 #define FLX_CSTAT_SHIFT 2 948 #define FLX_CSTAT_OKAY 0x0 949 #define FLX_CSTAT_OVER 0x1 950 #define FLX_CSTAT_UNDER 0x2 951 #define FLX_CSTAT_INVALID 0x3 952 953 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 954 u_int start_addr, u_int count, int bstream); 955 956 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 957 u_int start_addr, u_int count); 958 int ahd_wait_seeprom(struct ahd_softc *ahd); 959 int ahd_verify_vpd_cksum(struct vpd_config *vpd); 960 int ahd_verify_cksum(struct seeprom_config *sc); 961 int ahd_acquire_seeprom(struct ahd_softc *ahd); 962 void ahd_release_seeprom(struct ahd_softc *ahd); 963 964 /**************************** Message Buffer *********************************/ 965 typedef enum { 966 MSG_FLAG_NONE = 0x00, 967 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 968 MSG_FLAG_IU_REQ_CHANGED = 0x02, 969 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 970 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 971 MSG_FLAG_PACKETIZED = 0x10 972 } ahd_msg_flags; 973 974 typedef enum { 975 MSG_TYPE_NONE = 0x00, 976 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 977 MSG_TYPE_INITIATOR_MSGIN = 0x02, 978 MSG_TYPE_TARGET_MSGOUT = 0x03, 979 MSG_TYPE_TARGET_MSGIN = 0x04 980 } ahd_msg_type; 981 982 typedef enum { 983 MSGLOOP_IN_PROG, 984 MSGLOOP_MSGCOMPLETE, 985 MSGLOOP_TERMINATED 986 } msg_loop_stat; 987 988 /*********************** Software Configuration Structure *********************/ 989 struct ahd_suspend_channel_state { 990 uint8_t scsiseq; 991 uint8_t sxfrctl0; 992 uint8_t sxfrctl1; 993 uint8_t simode0; 994 uint8_t simode1; 995 uint8_t seltimer; 996 uint8_t seqctl; 997 }; 998 999 struct ahd_suspend_state { 1000 struct ahd_suspend_channel_state channel[2]; 1001 uint8_t optionmode; 1002 uint8_t dscommand0; 1003 uint8_t dspcistatus; 1004 /* hsmailbox */ 1005 uint8_t crccontrol1; 1006 uint8_t scbbaddr; 1007 /* Host and sequencer SCB counts */ 1008 uint8_t dff_thrsh; 1009 uint8_t *scratch_ram; 1010 uint8_t *btt; 1011 }; 1012 1013 typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1014 1015 typedef enum { 1016 AHD_MODE_DFF0, 1017 AHD_MODE_DFF1, 1018 AHD_MODE_CCHAN, 1019 AHD_MODE_SCSI, 1020 AHD_MODE_CFG, 1021 AHD_MODE_UNKNOWN 1022 } ahd_mode; 1023 1024 #define AHD_MK_MSK(x) (0x01 << (x)) 1025 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1026 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1027 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1028 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1029 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1030 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1031 #define AHD_MODE_ANY_MSK (~0) 1032 1033 typedef uint8_t ahd_mode_state; 1034 1035 typedef void ahd_callback_t (void *); 1036 1037 struct ahd_completion { 1038 uint16_t tag; 1039 uint8_t sg_status; 1040 uint8_t valid_tag; 1041 }; 1042 1043 #define AIC_SCB_DATA(softc) (&(softc)->scb_data) 1044 1045 struct ahd_softc { 1046 struct device sc_dev; 1047 struct device * sc_child; 1048 1049 bus_space_tag_t tags[2]; 1050 bus_space_handle_t bshs[2]; 1051 1052 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1053 struct scb_data scb_data; 1054 1055 struct hardware_scb *next_queued_hscb; 1056 struct map_node *next_queued_hscb_map; 1057 1058 /* 1059 * SCBs that have been sent to the controller 1060 */ 1061 TAILQ_HEAD(, scb) pending_scbs; 1062 1063 /* 1064 * SCBs whose timeout routine has been called. 1065 */ 1066 LIST_HEAD(, scb) timedout_scbs; 1067 1068 struct mutex sc_scb_mtx; 1069 struct scsi_iopool sc_iopool; 1070 1071 /* 1072 * Current register window mode information. 1073 */ 1074 ahd_mode dst_mode; 1075 ahd_mode src_mode; 1076 1077 /* 1078 * Saved register window mode information 1079 * used for restore on next unpause. 1080 */ 1081 ahd_mode saved_dst_mode; 1082 ahd_mode saved_src_mode; 1083 1084 /* 1085 * Platform specific device information. 1086 */ 1087 ahd_dev_softc_t dev_softc; 1088 1089 /* 1090 * Bus specific device information. 1091 */ 1092 ahd_bus_intr_t bus_intr; 1093 1094 /* 1095 * Target mode related state kept on a per enabled lun basis. 1096 * Targets that are not enabled will have null entries. 1097 * As an initiator, we keep one target entry for our initiator 1098 * ID to store our sync/wide transfer settings. 1099 */ 1100 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1101 1102 char inited_target[AHD_NUM_TARGETS]; 1103 1104 /* 1105 * The black hole device responsible for handling requests for 1106 * disabled luns on enabled targets. 1107 */ 1108 struct ahd_tmode_lstate *black_hole; 1109 1110 /* 1111 * Device instance currently on the bus awaiting a continue TIO 1112 * for a command that was not given the disconnect privilege. 1113 */ 1114 struct ahd_tmode_lstate *pending_device; 1115 1116 /* 1117 * Timer handles for timer driven callbacks. 1118 */ 1119 aic_timer_t reset_timer; 1120 aic_timer_t stat_timer; 1121 1122 /* 1123 * Statistics. 1124 */ 1125 #define AHD_STAT_UPDATE_MS 250 1126 #define AHD_STAT_BUCKETS 4 1127 u_int cmdcmplt_bucket; 1128 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1129 uint32_t cmdcmplt_total; 1130 1131 /* 1132 * Card characteristics 1133 */ 1134 ahd_chip chip; 1135 ahd_feature features; 1136 ahd_bug bugs; 1137 ahd_flag flags; 1138 struct seeprom_config *seep_config; 1139 1140 /* Command Queues */ 1141 struct ahd_completion *qoutfifo; 1142 uint16_t qoutfifonext; 1143 uint16_t qoutfifonext_valid_tag; 1144 uint16_t qinfifonext; 1145 uint16_t qinfifo[AHD_SCB_MAX]; 1146 1147 /* 1148 * Our qfreeze count. The sequencer compares 1149 * this value with its own counter to determine 1150 * whether to allow selections to occur. 1151 */ 1152 uint16_t qfreeze_cnt; 1153 1154 /* Values to store in the SEQCTL register for pause and unpause */ 1155 uint8_t unpause; 1156 uint8_t pause; 1157 1158 /* Critical Section Data */ 1159 struct cs *critical_sections; 1160 u_int num_critical_sections; 1161 1162 /* Buffer for handling packetized bitbucket. */ 1163 uint8_t *overrun_buf; 1164 1165 /* Links for chaining softcs */ 1166 TAILQ_ENTRY(ahd_softc) links; 1167 1168 /* Channel Names ('A', 'B', etc.) */ 1169 char channel; 1170 1171 /* Initiator Bus ID */ 1172 uint8_t our_id; 1173 1174 /* 1175 * Target incoming command FIFO. 1176 */ 1177 struct target_cmd *targetcmds; 1178 uint8_t tqinfifonext; 1179 1180 /* 1181 * Cached version of the hs_mailbox so we can avoid 1182 * pausing the sequencer during mailbox updates. 1183 */ 1184 uint8_t hs_mailbox; 1185 1186 /* 1187 * Incoming and outgoing message handling. 1188 */ 1189 uint8_t send_msg_perror; 1190 ahd_msg_flags msg_flags; 1191 ahd_msg_type msg_type; 1192 uint8_t msgout_buf[12];/* Message we are sending */ 1193 uint8_t msgin_buf[12];/* Message we are receiving */ 1194 u_int msgout_len; /* Length of message to send */ 1195 u_int msgout_index; /* Current index in msgout */ 1196 u_int msgin_index; /* Current index in msgin */ 1197 1198 /* 1199 * Mapping information for data structures shared 1200 * between the sequencer and kernel. 1201 */ 1202 bus_dma_tag_t parent_dmat; 1203 struct map_node shared_data_map; 1204 1205 /* Information saved through suspend/resume cycles */ 1206 struct ahd_suspend_state suspend_state; 1207 1208 /* Number of enabled target mode device on this card */ 1209 u_int enabled_luns; 1210 1211 /* Initialization level of this data structure */ 1212 u_int init_level; 1213 1214 /* PCI cacheline size. */ 1215 u_int pci_cachesize; 1216 1217 /* IO Cell Parameters */ 1218 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1219 1220 u_int stack_size; 1221 uint16_t *saved_stack; 1222 1223 /* Per-Unit descriptive information */ 1224 const char *bus_description; 1225 char *name; 1226 int unit; 1227 1228 /* Selection Timer settings */ 1229 int seltime; 1230 1231 /* 1232 * Interrupt coalescing settings. 1233 */ 1234 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1235 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1236 #define AHD_INT_COALESCING_MAXCMDS_MAX 127 1237 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1238 #define AHD_INT_COALESCING_MINCMDS_MAX 127 1239 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1240 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1241 u_int int_coalescing_timer; 1242 u_int int_coalescing_maxcmds; 1243 u_int int_coalescing_mincmds; 1244 u_int int_coalescing_threshold; 1245 u_int int_coalescing_stop_threshold; 1246 1247 uint16_t user_discenable;/* Disconnection allowed */ 1248 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1249 1250 /* Adapter interrupt routine */ 1251 void *ih; 1252 int pcix_off; 1253 }; 1254 1255 TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1256 extern struct ahd_softc_tailq ahd_tailq; 1257 1258 /*************************** IO Cell Configuration ****************************/ 1259 #define AHD_PRECOMP_SLEW_INDEX \ 1260 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1261 1262 #define AHD_AMPLITUDE_INDEX \ 1263 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1264 1265 #define AHD_SET_SLEWRATE(ahd, new_slew) \ 1266 do { \ 1267 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1268 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1269 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1270 } while (0) 1271 1272 #define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1273 do { \ 1274 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1275 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1276 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1277 } while (0) 1278 1279 #define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1280 do { \ 1281 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1282 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1283 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1284 } while (0) 1285 1286 /************************ Active Device Information ***************************/ 1287 typedef enum { 1288 ROLE_UNKNOWN, 1289 ROLE_INITIATOR, 1290 ROLE_TARGET 1291 } role_t; 1292 1293 struct ahd_devinfo { 1294 int our_scsiid; 1295 int target_offset; 1296 uint16_t target_mask; 1297 u_int target; 1298 u_int lun; 1299 char channel; 1300 role_t role; /* 1301 * Only guaranteed to be correct if not 1302 * in the busfree state. 1303 */ 1304 }; 1305 1306 /****************************** PCI Structures ********************************/ 1307 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O BAR*/ 1308 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */ 1309 #define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */ 1310 1311 typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *pa); 1312 1313 struct ahd_pci_identity { 1314 uint64_t full_id; 1315 uint64_t id_mask; 1316 ahd_device_setup_t *setup; 1317 }; 1318 extern const struct ahd_pci_identity ahd_pci_ident_table[]; 1319 extern const u_int ahd_num_pci_devs; 1320 1321 /*************************** Function Declarations ****************************/ 1322 /******************************************************************************/ 1323 void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1324 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1325 void ahd_busy_tcl(struct ahd_softc *ahd, 1326 u_int tcl, u_int busyid); 1327 void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1328 1329 /***************************** PCI Front End *********************************/ 1330 const struct ahd_pci_identity * ahd_find_pci_device(pcireg_t, pcireg_t); 1331 int ahd_pci_test_register_access(struct ahd_softc *); 1332 1333 /************************** SCB and SCB queue management **********************/ 1334 int ahd_probe_scbs(struct ahd_softc *); 1335 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1336 struct scb *scb); 1337 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1338 int target, char channel, int lun, 1339 u_int tag, role_t role); 1340 1341 /****************************** Initialization ********************************/ 1342 struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1343 int ahd_softc_init(struct ahd_softc *); 1344 void ahd_controller_info(struct ahd_softc *ahd, char *buf, 1345 size_t bufsz); 1346 int ahd_init(struct ahd_softc *ahd); 1347 int ahd_default_config(struct ahd_softc *ahd); 1348 int ahd_parse_vpddata(struct ahd_softc *ahd, 1349 struct vpd_config *vpd); 1350 int ahd_parse_cfgdata(struct ahd_softc *ahd, 1351 struct seeprom_config *sc); 1352 void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1353 void ahd_update_coalescing_values(struct ahd_softc *ahd, 1354 u_int timer, 1355 u_int maxcmds, 1356 u_int mincmds); 1357 void ahd_enable_coalescing(struct ahd_softc *ahd, 1358 int enable); 1359 void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1360 int ahd_suspend(struct ahd_softc *ahd); 1361 int ahd_resume(struct ahd_softc *ahd); 1362 void ahd_softc_insert(struct ahd_softc *); 1363 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1364 void ahd_set_unit(struct ahd_softc *, int); 1365 void ahd_set_name(struct ahd_softc *, char *); 1366 void *ahd_scb_alloc(void *); 1367 void ahd_scb_free(void *, void *); 1368 void ahd_alloc_scbs(struct ahd_softc *ahd); 1369 void ahd_free(struct ahd_softc *ahd); 1370 int ahd_reset(struct ahd_softc *ahd, int reinit); 1371 void ahd_shutdown(void *arg); 1372 int ahd_write_flexport(struct ahd_softc *ahd, 1373 u_int addr, u_int value); 1374 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1375 uint8_t *value); 1376 int ahd_wait_flexport(struct ahd_softc *ahd); 1377 1378 /*************************** Interrupt Services *******************************/ 1379 void ahd_pci_intr(struct ahd_softc *ahd); 1380 void ahd_clear_intstat(struct ahd_softc *ahd); 1381 void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1382 void ahd_run_qoutfifo(struct ahd_softc *ahd); 1383 #ifdef AHD_TARGET_MODE 1384 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1385 #endif 1386 void ahd_handle_hwerrint(struct ahd_softc *ahd); 1387 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1388 void ahd_handle_scsiint(struct ahd_softc *ahd, 1389 u_int intstat); 1390 void ahd_clear_critical_section(struct ahd_softc *ahd); 1391 1392 /***************************** Error Recovery *********************************/ 1393 typedef enum { 1394 SEARCH_COMPLETE, 1395 SEARCH_COUNT, 1396 SEARCH_REMOVE, 1397 SEARCH_PRINT 1398 } ahd_search_action; 1399 void ahd_done_with_status(struct ahd_softc *ahd, 1400 struct scb *scb, uint32_t status); 1401 int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1402 char channel, int lun, u_int tag, 1403 role_t role, uint32_t status, 1404 ahd_search_action action); 1405 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1406 int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1407 int initiate_reset); 1408 int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1409 char channel, int lun, u_int tag, 1410 role_t role, uint32_t status); 1411 void ahd_restart(struct ahd_softc *ahd); 1412 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1413 void ahd_handle_scb_status(struct ahd_softc *ahd, 1414 struct scb *scb); 1415 void ahd_handle_scsi_status(struct ahd_softc *ahd, 1416 struct scb *scb); 1417 void ahd_calc_residual(struct ahd_softc *ahd, 1418 struct scb *scb); 1419 void ahd_timeout(void *); 1420 /*************************** Utility Functions ********************************/ 1421 struct ahd_phase_table_entry* 1422 ahd_lookup_phase_entry(int phase); 1423 void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1424 u_int our_id, u_int target, 1425 u_int lun, char channel, 1426 role_t role); 1427 /************************** Transfer Negotiation ******************************/ 1428 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1429 u_int *ppr_options, u_int maxsync); 1430 void ahd_validate_offset(struct ahd_softc *ahd, 1431 struct ahd_initiator_tinfo *tinfo, 1432 u_int period, u_int *offset, 1433 int wide, role_t role); 1434 void ahd_validate_width(struct ahd_softc *ahd, 1435 struct ahd_initiator_tinfo *tinfo, 1436 u_int *bus_width, 1437 role_t role); 1438 void ahd_scb_devinfo(struct ahd_softc *, 1439 struct ahd_devinfo *, struct scb *); 1440 1441 /* 1442 * Negotiation types. These are used to qualify if we should renegotiate 1443 * even if our goal and current transport parameters are identical. 1444 */ 1445 typedef enum { 1446 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1447 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1448 AHD_NEG_ALWAYS /* Renegotiate even if goal is async. */ 1449 } ahd_neg_type; 1450 int ahd_update_neg_request(struct ahd_softc*, 1451 struct ahd_devinfo*, 1452 struct ahd_tmode_tstate*, 1453 struct ahd_initiator_tinfo*, 1454 ahd_neg_type); 1455 void ahd_set_width(struct ahd_softc *ahd, 1456 struct ahd_devinfo *devinfo, 1457 u_int width, u_int type, int paused); 1458 void ahd_set_syncrate(struct ahd_softc *ahd, 1459 struct ahd_devinfo *devinfo, 1460 u_int period, u_int offset, 1461 u_int ppr_options, 1462 u_int type, int paused); 1463 typedef enum { 1464 AHD_QUEUE_NONE, 1465 AHD_QUEUE_BASIC, 1466 AHD_QUEUE_TAGGED 1467 } ahd_queue_alg; 1468 1469 void ahd_set_tags(struct ahd_softc *ahd, 1470 struct ahd_devinfo *devinfo, 1471 ahd_queue_alg alg); 1472 1473 /**************************** Target Mode *************************************/ 1474 #ifdef AHD_TARGET_MODE 1475 void ahd_send_lstate_events(struct ahd_softc *, 1476 struct ahd_tmode_lstate *); 1477 void ahd_handle_en_lun(struct ahd_softc *ahd, 1478 struct cam_sim *sim, union ccb *ccb); 1479 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1480 struct cam_sim *sim, union ccb *ccb, 1481 struct ahd_tmode_tstate **tstate, 1482 struct ahd_tmode_lstate **lstate, 1483 int notfound_failure); 1484 #ifndef AHD_TMODE_ENABLE 1485 #define AHD_TMODE_ENABLE 0 1486 #endif 1487 #endif 1488 /******************************* Debug ***************************************/ 1489 #ifdef AHD_DEBUG 1490 extern uint32_t ahd_debug; 1491 #define AHD_DEBUG_OPTS 0 1492 #define AHD_SHOW_MISC 0x00001 1493 #define AHD_SHOW_SENSE 0x00002 1494 #define AHD_SHOW_RECOVERY 0x00004 1495 #define AHD_DUMP_SEEPROM 0x00008 1496 #define AHD_SHOW_TERMCTL 0x00010 1497 #define AHD_SHOW_MEMORY 0x00020 1498 #define AHD_SHOW_MESSAGES 0x00040 1499 #define AHD_SHOW_MODEPTR 0x00080 1500 #define AHD_SHOW_SELTO 0x00100 1501 #define AHD_SHOW_FIFOS 0x00200 1502 #define AHD_SHOW_QFULL 0x00400 1503 #define AHD_SHOW_DV 0x00800 1504 #define AHD_SHOW_MASKED_ERRORS 0x01000 1505 #define AHD_SHOW_QUEUE 0x02000 1506 #define AHD_SHOW_TQIN 0x04000 1507 #define AHD_SHOW_SG 0x08000 1508 #define AHD_SHOW_INT_COALESCING 0x10000 1509 #define AHD_DEBUG_SEQUENCER 0x20000 1510 #endif 1511 void ahd_print_scb(struct scb *scb); 1512 void ahd_print_devinfo(struct ahd_softc *ahd, 1513 struct ahd_devinfo *devinfo); 1514 void ahd_dump_sglist(struct scb *scb); 1515 void ahd_dump_all_cards_state(void); 1516 void ahd_dump_card_state(struct ahd_softc *ahd); 1517 int ahd_print_register(ahd_reg_parse_entry_t *table, 1518 u_int num_entries, 1519 const char *name, 1520 u_int address, 1521 u_int value, 1522 u_int *cur_column, 1523 u_int wrap_point); 1524 void ahd_dump_scbs(struct ahd_softc *ahd); 1525 1526 #endif /* _AIC79XX_H_ */ 1527