1 /* $OpenBSD: envyreg.h,v 1.20 2022/01/09 05:42:45 jsg Exp $ */ 2 /* 3 * Copyright (c) 2007 Alexandre Ratchov <alex@caoua.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #ifndef SYS_DEV_PCI_ENVYREG_H 18 #define SYS_DEV_PCI_ENVYREG_H 19 20 /* 21 * BARs at PCI config space 22 */ 23 #define ENVY_CTL_BAR 0x10 24 #define ENVY_MT_BAR(isht) ((isht) ? 0x14 : 0x1c) 25 #define ENVY_CONF 0x60 26 27 /* 28 * CCS "control" register 29 */ 30 #define ENVY_CTL 0x00 31 #define ENVY_CTL_RESET 0x80 32 #define ENVY_CTL_NATIVE 0x01 33 #define ENVY_CCS_INTMASK 0x01 34 #define ENVY_CCS_INT_MT 0x10 35 #define ENVY_CCS_INT_MIDI0 0x80 36 #define ENVY_CCS_INT_MIDI1 0x20 /* Envy24 only */ 37 #define ENVY_CCS_INTSTAT 0x02 38 #define ENVY_CCS_CONF 0x04 /* Envy24HT only */ 39 #define ENVY_CCS_ACLINK 0x05 /* Envy24HT only */ 40 #define ENVY_CCS_I2S 0x06 /* Envy24HT only */ 41 #define ENVY_CCS_SPDIF 0x07 /* Envy24HT only */ 42 #define ENVY_CCS_MIDIDATA0 0x0c 43 #define ENVY_CCS_MIDISTAT0 0x0d 44 #define ENVY_CCS_MIDIDATA1 0x1c /* Envy24 only */ 45 #define ENVY_CCS_MIDISTAT1 0x1d /* Envy24 only */ 46 #define ENVY_CCS_MIDIWAT 0x0e /* Envy24HT only */ 47 #define ENVY_CCS_MIDIWAT_RX 0x20 48 #define ENVY_CCS_MIDIDATA1 0x1c 49 #define ENVY_CCS_MIDISTAT1 0x1d 50 #define ENVY_CCS_GPIODATA0 0x14 /* Envy24HT only */ 51 #define ENVY_CCS_GPIODATA1 0x15 /* Envy24HT only */ 52 #define ENVY_CCS_GPIODATA2 0x1e /* Envy24HT only */ 53 #define ENVY_CCS_GPIOMASK0 0x16 /* Envy24HT only */ 54 #define ENVY_CCS_GPIOMASK1 0x17 /* Envy24HT only */ 55 #define ENVY_CCS_GPIOMASK2 0x1f /* Envy24HT only */ 56 #define ENVY_CCS_GPIODIR0 0x18 /* Envy24HT only */ 57 #define ENVY_CCS_GPIODIR1 0x19 /* Envy24HT only */ 58 #define ENVY_CCS_GPIODIR2 0x1a /* Envy24HT only */ 59 60 /* 61 * CCS registers to access indirect registers (CCI) 62 */ 63 #define ENVY_CCI_INDEX 0x3 64 #define ENVY_CCI_DATA 0x4 65 66 /* 67 * CCS registers to access iic bus 68 */ 69 #define ENVY_I2C_DEV 0x10 70 #define ENVY_I2C_DEV_SHIFT 0x01 71 #define ENVY_I2C_DEV_WRITE 0x01 72 #define ENVY_I2C_DEV_EEPROM 0x50 73 #define ENVY_I2C_ADDR 0x11 74 #define ENVY_I2C_DATA 0x12 75 #define ENVY_I2C_CTL 0x13 76 #define ENVY_I2C_CTL_BUSY 0x1 77 78 /* 79 * CCI registers to access GPIO pins 80 */ 81 #define ENVY_CCI_GPIODATA 0x20 82 #define ENVY_CCI_GPIOMASK 0x21 83 #define ENVY_CCI_GPIODIR 0x22 84 85 /* 86 * EEPROM bytes signification 87 */ 88 #define ENVY_EEPROM_CONF 6 89 #define ENVY_CONF_MIDI 0x20 90 #define ENVY_EEPROM_ACLINK 7 91 #define ENVY_EEPROM_I2S 8 92 #define ENVY_EEPROM_SPDIF 9 93 #define ENVY_EEPROM_GPIOMASK(s) ((s)->isht ? 13 : 10) 94 #define ENVY_EEPROM_GPIOST(s) ((s)->isht ? 16 : 11) 95 #define ENVY_EEPROM_GPIODIR(s) ((s)->isht ? 10 : 12) 96 97 /* 98 * MIDI status 99 */ 100 #define ENVY_MIDISTAT_IEMPTY(s) ((s)->isht ? 0x8 : 0x80) 101 #define ENVY_MIDISTAT_OBUSY(s) ((s)->isht ? 0x4 : 0x40) 102 #define ENVY_MIDISTAT_RESET 0xff 103 #define ENVY_MIDISTAT_UART 0x3f 104 105 /* 106 * MT registers for play/record params 107 */ 108 #define ENVY_MT_INTR 0 109 #define ENVY_MT_INTR_PACK 0x01 110 #define ENVY_MT_INTR_RACK 0x02 111 #define ENVY_MT_INTR_ERR 0x08 /* fifo error on HT, else reads 0 */ 112 #define ENVY_MT_INTR_ALL 0x0b /* all of above */ 113 #define ENVY_MT_INTR_PMASK 0x40 /* !HT only */ 114 #define ENVY_MT_INTR_RMASK 0x80 /* !HT only */ 115 #define ENVY_MT_RATE 1 116 #define ENVY_MT_RATEMASK 0x0f 117 #define ENVY_MT_FMT 2 118 #define ENVY_MT_FMT_128X 0x08 /* HT only */ 119 #define ENVY_MT_IMASK 3 /* HT only */ 120 #define ENVY_MT_IMASK_PDMA0 0x1 121 #define ENVY_MT_IMASK_RDMA0 0x2 122 #define ENVY_MT_IMASK_ERR 0x8 123 #define ENVY_MT_AC97_IDX 4 124 #define ENVY_MT_AC97_CMD 5 125 #define ENVY_MT_AC97_READY 0x08 126 #define ENVY_MT_AC97_CMD_MASK 0x30 127 #define ENVY_MT_AC97_CMD_RD 0x10 128 #define ENVY_MT_AC97_CMD_WR 0x20 129 #define ENVY_MT_AC97_CMD_RST 0x80 130 #define ENVY_MT_AC97_DATA 6 131 #define ENVY_MT_PADDR 0x10 132 #define ENVY_MT_PBUFSZ 0x14 133 #define ENVY_MT_PBLKSZ(s) ((s)->isht ? 0x1c : 0x16) 134 #define ENVY_MT_CTL 0x18 135 #define ENVY_MT_CTL_PSTART 0x01 136 #define ENVY_MT_CTL_RSTART(s) ((s)->isht ? 0x02 : 0x04) 137 #define ENVY_MT_NSTREAM 0x19 /* HT only: 4 - active DACs */ 138 #define ENVY_MT_ERR 0x1a /* HT only: fifo error */ 139 #define ENVY_MT_RADDR 0x20 140 #define ENVY_MT_RBUFSZ 0x24 141 #define ENVY_MT_RBLKSZ 0x26 142 143 /* 144 * MT registers for monitor gains 145 */ 146 #define ENVY_MT_MONDATA 0x38 147 #define ENVY_MT_MONVAL_BITS 7 148 #define ENVY_MT_MONVAL_MASK ((1 << ENVY_MT_MONVAL_BITS) - 1) 149 #define ENVY_MT_MONIDX 0x3a 150 151 /* 152 * MT registers to access the digital mixer 153 */ 154 #define ENVY_MT_OUTSRC 0x30 155 #define ENVY_MT_OUTSRC_DMA 0x00 156 #define ENVY_MT_OUTSRC_MON 0x01 157 #define ENVY_MT_OUTSRC_LINE 0x02 158 #define ENVY_MT_OUTSRC_SPD 0x03 159 #define ENVY_MT_OUTSRC_MASK 0x03 160 #define ENVY_MT_SPDROUTE 0x32 161 #define ENVY_MT_SPDSRC_DMA 0x00 162 #define ENVY_MT_SPDSRC_MON 0x01 163 #define ENVY_MT_SPDSRC_LINE 0x02 164 #define ENVY_MT_SPDSRC_SPD 0x03 165 #define ENVY_MT_SPDSRC_BITS 0x02 166 #define ENVY_MT_SPDSRC_MASK ((1 << ENVY_MT_SPDSRC_BITS) - 1) 167 #define ENVY_MT_SPDSEL_BITS 0x4 168 #define ENVY_MT_SPDSEL_MASK ((1 << ENVY_MT_SPDSEL_BITS) - 1) 169 #define ENVY_MT_INSEL 0x34 170 #define ENVY_MT_INSEL_BITS 0x4 171 #define ENVY_MT_INSEL_MASK ((1 << ENVY_MT_INSEL_BITS) - 1) 172 173 /* 174 * HT routing control 175 */ 176 #define ENVY_MT_HTSRC 0x2c 177 #define ENVY_MT_HTSRC_DMA 0x00 178 #define ENVY_MT_HTSRC_LINE 0x02 179 #define ENVY_MT_HTSRC_SPD 0x04 180 #define ENVY_MT_HTSRC_MASK 0x07 181 182 /* 183 * AK4524 control registers 184 */ 185 #define AK4524_PWR 0x00 186 #define AK4524_PWR_DA 0x01 187 #define AK4524_PWR_AD 0x02 188 #define AK4524_PWR_VREF 0x04 189 #define AK4524_RST 0x01 190 #define AK4524_RST_DA 0x01 191 #define AK4524_RST_AD 0x02 192 #define AK4524_FMT 0x02 193 #define AK4524_FMT_NORM 0 194 #define AK4524_FMT_DBL 0x01 195 #define AK4524_FMT_QUA 0x02 196 #define AK4524_FMT_QAUDFILT 0x04 197 #define AK4524_FMT_256 0 198 #define AK4524_FMT_512 0x04 199 #define AK4524_FMT_1024 0x08 200 #define AK4524_FMT_384 0x10 201 #define AK4524_FMT_768 0x14 202 #define AK4524_FMT_LSB16 0 203 #define AK4524_FMT_LSB20 0x20 204 #define AK4524_FMT_MSB24 0x40 205 #define AK4524_FMT_IIS24 0x60 206 #define AK4524_FMT_LSB24 0x80 207 #define AK4524_DEEMVOL 0x03 208 #define AK4524_DEEM_44K1 0x00 209 #define AK4524_DEEM_OFF 0x01 210 #define AK4524_DEEM_48K 0x02 211 #define AK4524_DEEM_32K 0x03 212 #define AK4524_MUTE 0x80 213 #define AK4524_ADC_GAIN0 0x04 214 #define AK4524_ADC_GAIN1 0x05 215 #define AK4524_DAC_GAIN0 0x06 216 #define AK4524_DAC_GAIN1 0x07 217 218 /* 219 * AK4358 control registers 220 */ 221 #define AK4358_ATT(chan) ((chan) <= 5 ? 0x4 + (chan) : 0xb - 6 + (chan)) 222 #define AK4358_ATT_EN 0x80 223 #define AK4358_SPEED 2 224 #define AK4358_SPEED_RSTN 0x01 /* 0 = reset, 1 = normal op */ 225 #define AK4358_SPEED_PW1 0x02 /* power-down dac1 */ 226 #define AK4358_SPEED_PW2 0x04 /* power-down dac2 */ 227 #define AK4358_SPEED_PW3 0x08 /* power-down dac3 */ 228 #define AK4358_SPEED_DFS0 0x10 /* rate multiplier (1x, 2x, 4x) */ 229 #define AK4358_SPEED_DFS1 0x20 230 #define AK4358_SPEED_PW4 0x40 /* power-down dac4 */ 231 #define AK4358_SPEED_DEFAULT 0x4f /* default register value */ 232 233 /* 234 * AK5365 control registers 235 */ 236 #define AK5365_RST 0x00 237 #define AK5365_RST_NORM 0x01 238 #define AK5365_SRC 0x01 239 #define AK5365_SRC_MASK 0x07 240 #define AK5365_CTRL 0x02 241 #define AK5365_CTRL_MUTE 0x01 242 #define AK5365_CTRL_I2S 0x08 243 #define AK5365_ATT(chan) (0x4 + (chan)) 244 245 /* 246 * default formats 247 */ 248 #define ENVY_RCHANS 12 249 #define ENVY_PCHANS 10 250 #define ENVY_RFRAME_SIZE (4 * ENVY_RCHANS) 251 #define ENVY_PFRAME_SIZE (4 * ENVY_PCHANS) 252 253 #endif /* !defined(SYS_DEV_PCI_ENVYREG_H) */ 254