1 /* $OpenBSD: if_alereg.h,v 1.4 2022/01/09 05:42:46 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ale/if_alereg.h,v 1.1 2008/11/12 09:52:06 yongari Exp $ 29 */ 30 31 #ifndef _IF_ALEREG_H 32 #define _IF_ALEREG_H 33 34 #define ALE_PCIR_BAR 0x10 35 36 #define ALE_SPI_CTRL 0x200 37 #define SPI_VPD_ENB 0x00002000 38 39 #define ALE_SPI_ADDR 0x204 /* 16bits */ 40 41 #define ALE_SPI_DATA 0x208 42 43 #define ALE_SPI_CONFIG 0x20C 44 45 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ 46 47 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 48 49 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 50 51 #define ALE_SPI_OP_RDID 0x213 /* 8bits */ 52 53 #define ALE_SPI_OP_WREN 0x214 /* 8bits */ 54 55 #define ALE_SPI_OP_RDSR 0x215 /* 8bits */ 56 57 #define ALE_SPI_OP_WRSR 0x216 /* 8bits */ 58 59 #define ALE_SPI_OP_READ 0x217 /* 8bits */ 60 61 #define ALE_TWSI_CTRL 0x218 62 #define TWSI_CTRL_SW_LD_START 0x00000800 63 #define TWSI_CTRL_HW_LD_START 0x00001000 64 #define TWSI_CTRL_LD_EXIST 0x00400000 65 66 #define ALE_DEV_MISC_CTRL 0x21C 67 68 #define ALE_PCIE_PHYMISC 0x1000 69 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 70 71 #define ALE_MASTER_CFG 0x1400 72 #define MASTER_RESET 0x00000001 73 #define MASTER_MTIMER_ENB 0x00000002 74 #define MASTER_IM_TX_TIMER_ENB 0x00000004 75 #define MASTER_MANUAL_INT_ENB 0x00000008 76 #define MASTER_IM_RX_TIMER_ENB 0x00000020 77 #define MASTER_INT_RDCLR 0x00000040 78 #define MASTER_LED_MODE 0x00000200 79 #define MASTER_CHIP_REV_MASK 0x00FF0000 80 #define MASTER_CHIP_ID_MASK 0xFF000000 81 #define MASTER_CHIP_REV_SHIFT 16 82 #define MASTER_CHIP_ID_SHIFT 24 83 84 /* Number of ticks per usec for AR81xx. */ 85 #define ALE_TICK_USECS 2 86 #define ALE_USECS(x) ((x) / ALE_TICK_USECS) 87 88 #define ALE_MANUAL_TIMER 0x1404 89 90 #define ALE_IM_TIMER 0x1408 91 #define IM_TIMER_TX_MASK 0x0000FFFF 92 #define IM_TIMER_RX_MASK 0xFFFF0000 93 #define IM_TIMER_TX_SHIFT 0 94 #define IM_TIMER_RX_SHIFT 16 95 #define ALE_IM_TIMER_MIN 0 96 #define ALE_IM_TIMER_MAX 130000 /* 130ms */ 97 #define ALE_IM_RX_TIMER_DEFAULT 30 98 #define ALE_IM_TX_TIMER_DEFAULT 1000 99 100 #define ALE_GPHY_CTRL 0x140C /* 16bits */ 101 #define GPHY_CTRL_EXT_RESET 0x0001 102 #define GPHY_CTRL_PIPE_MOD 0x0002 103 #define GPHY_CTRL_BERT_START 0x0010 104 #define GPHY_CTRL_GALE_25M_ENB 0x0020 105 #define GPHY_CTRL_LPW_EXIT 0x0040 106 #define GPHY_CTRL_PHY_IDDQ 0x0080 107 #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 108 #define GPHY_CTRL_PCLK_SEL_DIS 0x0200 109 #define GPHY_CTRL_HIB_EN 0x0400 110 #define GPHY_CTRL_HIB_PULSE 0x0800 111 #define GPHY_CTRL_SEL_ANA_RESET 0x1000 112 #define GPHY_CTRL_PHY_PLL_ON 0x2000 113 #define GPHY_CTRL_PWDOWN_HW 0x4000 114 115 #define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ 116 117 #define ALE_IDLE_STATUS 0x1410 118 #define IDLE_STATUS_RXMAC 0x00000001 119 #define IDLE_STATUS_TXMAC 0x00000002 120 #define IDLE_STATUS_RXQ 0x00000004 121 #define IDLE_STATUS_TXQ 0x00000008 122 #define IDLE_STATUS_DMARD 0x00000010 123 #define IDLE_STATUS_DMAWR 0x00000020 124 #define IDLE_STATUS_SMB 0x00000040 125 #define IDLE_STATUS_CMB 0x00000080 126 127 #define ALE_MDIO 0x1414 128 #define MDIO_DATA_MASK 0x0000FFFF 129 #define MDIO_REG_ADDR_MASK 0x001F0000 130 #define MDIO_OP_READ 0x00200000 131 #define MDIO_OP_WRITE 0x00000000 132 #define MDIO_SUP_PREAMBLE 0x00400000 133 #define MDIO_OP_EXECUTE 0x00800000 134 #define MDIO_CLK_25_4 0x00000000 135 #define MDIO_CLK_25_6 0x02000000 136 #define MDIO_CLK_25_8 0x03000000 137 #define MDIO_CLK_25_10 0x04000000 138 #define MDIO_CLK_25_14 0x05000000 139 #define MDIO_CLK_25_20 0x06000000 140 #define MDIO_CLK_25_28 0x07000000 141 #define MDIO_OP_BUSY 0x08000000 142 #define MDIO_DATA_SHIFT 0 143 #define MDIO_REG_ADDR_SHIFT 16 144 145 #define MDIO_REG_ADDR(x) \ 146 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 147 /* Default PHY address. */ 148 #define ALE_PHY_ADDR 0 149 150 #define ALE_PHY_STATUS 0x1418 151 #define PHY_STATUS_100M 0x00020000 152 153 /* Packet memory BIST. */ 154 #define ALE_BIST0 0x141C 155 #define BIST0_ENB 0x00000001 156 #define BIST0_SRAM_FAIL 0x00000002 157 #define BIST0_FUSE_FLAG 0x00000004 158 159 /* PCIe retry buffer BIST. */ 160 #define ALE_BIST1 0x1420 161 #define BIST1_ENB 0x00000001 162 #define BIST1_SRAM_FAIL 0x00000002 163 #define BIST1_FUSE_FLAG 0x00000004 164 165 #define ALE_SERDES_LOCK 0x1424 166 #define SERDES_LOCK_DET 0x00000001 167 #define SERDES_LOCK_DET_ENB 0x00000002 168 169 #define ALE_MAC_CFG 0x1480 170 #define MAC_CFG_TX_ENB 0x00000001 171 #define MAC_CFG_RX_ENB 0x00000002 172 #define MAC_CFG_TX_FC 0x00000004 173 #define MAC_CFG_RX_FC 0x00000008 174 #define MAC_CFG_LOOP 0x00000010 175 #define MAC_CFG_FULL_DUPLEX 0x00000020 176 #define MAC_CFG_TX_CRC_ENB 0x00000040 177 #define MAC_CFG_TX_AUTO_PAD 0x00000080 178 #define MAC_CFG_TX_LENCHK 0x00000100 179 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 180 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 181 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 182 #define MAC_CFG_PROMISC 0x00008000 183 #define MAC_CFG_TX_PAUSE 0x00010000 184 #define MAC_CFG_SCNT 0x00020000 185 #define MAC_CFG_SYNC_RST_TX 0x00040000 186 #define MAC_CFG_SPEED_MASK 0x00300000 187 #define MAC_CFG_SPEED_10_100 0x00100000 188 #define MAC_CFG_SPEED_1000 0x00200000 189 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 190 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 191 #define MAC_CFG_RXCSUM_ENB 0x01000000 192 #define MAC_CFG_ALLMULTI 0x02000000 193 #define MAC_CFG_BCAST 0x04000000 194 #define MAC_CFG_DBG 0x08000000 195 #define MAC_CFG_PREAMBLE_SHIFT 10 196 #define MAC_CFG_PREAMBLE_DEFAULT 7 197 198 #define ALE_IPG_IFG_CFG 0x1484 199 #define IPG_IFG_IPGT_MASK 0x0000007F 200 #define IPG_IFG_MIFG_MASK 0x0000FF00 201 #define IPG_IFG_IPG1_MASK 0x007F0000 202 #define IPG_IFG_IPG2_MASK 0x7F000000 203 #define IPG_IFG_IPGT_SHIFT 0 204 #define IPG_IFG_IPGT_DEFAULT 0x60 205 #define IPG_IFG_MIFG_SHIFT 8 206 #define IPG_IFG_MIFG_DEFAULT 0x50 207 #define IPG_IFG_IPG1_SHIFT 16 208 #define IPG_IFG_IPG1_DEFAULT 0x40 209 #define IPG_IFG_IPG2_SHIFT 24 210 #define IPG_IFG_IPG2_DEFAULT 0x60 211 212 /* Station address. */ 213 #define ALE_PAR0 0x1488 214 #define ALE_PAR1 0x148C 215 216 /* 64bit multicast hash register. */ 217 #define ALE_MAR0 0x1490 218 #define ALE_MAR1 0x1494 219 220 /* half-duplex parameter configuration. */ 221 #define ALE_HDPX_CFG 0x1498 222 #define HDPX_CFG_LCOL_MASK 0x000003FF 223 #define HDPX_CFG_RETRY_MASK 0x0000F000 224 #define HDPX_CFG_EXC_DEF_EN 0x00010000 225 #define HDPX_CFG_NO_BACK_C 0x00020000 226 #define HDPX_CFG_NO_BACK_P 0x00040000 227 #define HDPX_CFG_ABEBE 0x00080000 228 #define HDPX_CFG_ABEBT_MASK 0x00F00000 229 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 230 #define HDPX_CFG_LCOL_SHIFT 0 231 #define HDPX_CFG_LCOL_DEFAULT 0x37 232 #define HDPX_CFG_RETRY_SHIFT 12 233 #define HDPX_CFG_RETRY_DEFAULT 0x0F 234 #define HDPX_CFG_ABEBT_SHIFT 20 235 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 236 #define HDPX_CFG_JAMIPG_SHIFT 24 237 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 238 239 #define ALE_FRAME_SIZE 0x149C 240 241 #define ALE_WOL_CFG 0x14A0 242 #define WOL_CFG_PATTERN 0x00000001 243 #define WOL_CFG_PATTERN_ENB 0x00000002 244 #define WOL_CFG_MAGIC 0x00000004 245 #define WOL_CFG_MAGIC_ENB 0x00000008 246 #define WOL_CFG_LINK_CHG 0x00000010 247 #define WOL_CFG_LINK_CHG_ENB 0x00000020 248 #define WOL_CFG_PATTERN_DET 0x00000100 249 #define WOL_CFG_MAGIC_DET 0x00000200 250 #define WOL_CFG_LINK_CHG_DET 0x00000400 251 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 252 #define WOL_CFG_PATTERN0 0x00010000 253 #define WOL_CFG_PATTERN1 0x00020000 254 #define WOL_CFG_PATTERN2 0x00040000 255 #define WOL_CFG_PATTERN3 0x00080000 256 #define WOL_CFG_PATTERN4 0x00100000 257 #define WOL_CFG_PATTERN5 0x00200000 258 #define WOL_CFG_PATTERN6 0x00400000 259 260 /* WOL pattern length. */ 261 #define ALE_PATTERN_CFG0 0x14A4 262 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 263 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 264 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 265 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 266 267 #define ALE_PATTERN_CFG1 0x14A8 268 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 269 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 270 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 271 272 /* RSS */ 273 #define ALE_RSS_KEY0 0x14B0 274 275 #define ALE_RSS_KEY1 0x14B4 276 277 #define ALE_RSS_KEY2 0x14B8 278 279 #define ALE_RSS_KEY3 0x14BC 280 281 #define ALE_RSS_KEY4 0x14C0 282 283 #define ALE_RSS_KEY5 0x14C4 284 285 #define ALE_RSS_KEY6 0x14C8 286 287 #define ALE_RSS_KEY7 0x14CC 288 289 #define ALE_RSS_KEY8 0x14D0 290 291 #define ALE_RSS_KEY9 0x14D4 292 293 #define ALE_RSS_IDT_TABLE4 0x14E0 294 295 #define ALE_RSS_IDT_TABLE5 0x14E4 296 297 #define ALE_RSS_IDT_TABLE6 0x14E8 298 299 #define ALE_RSS_IDT_TABLE7 0x14EC 300 301 #define ALE_SRAM_RD_ADDR 0x1500 302 303 #define ALE_SRAM_RD_LEN 0x1504 304 305 #define ALE_SRAM_RRD_ADDR 0x1508 306 307 #define ALE_SRAM_RRD_LEN 0x150C 308 309 #define ALE_SRAM_TPD_ADDR 0x1510 310 311 #define ALE_SRAM_TPD_LEN 0x1514 312 313 #define ALE_SRAM_TRD_ADDR 0x1518 314 315 #define ALE_SRAM_TRD_LEN 0x151C 316 317 #define ALE_SRAM_RX_FIFO_ADDR 0x1520 318 319 #define ALE_SRAM_RX_FIFO_LEN 0x1524 320 321 #define ALE_SRAM_TX_FIFO_ADDR 0x1528 322 323 #define ALE_SRAM_TX_FIFO_LEN 0x152C 324 325 #define ALE_SRAM_TCPH_ADDR 0x1530 326 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 327 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 328 #define SRAM_TCPH_ADDR_SHIFT 0 329 #define SRAM_PATH_ADDR_SHIFT 16 330 331 #define ALE_DMA_BLOCK 0x1534 332 #define DMA_BLOCK_LOAD 0x00000001 333 334 #define ALE_RXF3_ADDR_HI 0x153C 335 336 #define ALE_TPD_ADDR_HI 0x1540 337 338 #define ALE_RXF0_PAGE0_ADDR_LO 0x1544 339 340 #define ALE_RXF0_PAGE1_ADDR_LO 0x1548 341 342 #define ALE_TPD_ADDR_LO 0x154C 343 344 #define ALE_RXF1_ADDR_HI 0x1550 345 346 #define ALE_RXF2_ADDR_HI 0x1554 347 348 #define ALE_RXF_PAGE_SIZE 0x1558 349 350 #define ALE_TPD_CNT 0x155C 351 #define TPD_CNT_MASK 0x00003FF 352 #define TPD_CNT_SHIFT 0 353 354 #define ALE_RSS_IDT_TABLE0 0x1560 355 356 #define ALE_RSS_IDT_TABLE1 0x1564 357 358 #define ALE_RSS_IDT_TABLE2 0x1568 359 360 #define ALE_RSS_IDT_TABLE3 0x156C 361 362 #define ALE_RSS_HASH_VALUE 0x1570 363 364 #define ALE_RSS_HASH_FLAG 0x1574 365 366 #define ALE_RSS_CPU 0x157C 367 368 #define ALE_TXQ_CFG 0x1580 369 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F 370 #define TXQ_CFG_ENB 0x00000020 371 #define TXQ_CFG_ENHANCED_MODE 0x00000040 372 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 373 #define TXQ_CFG_TPD_BURST_SHIFT 0 374 #define TXQ_CFG_TPD_BURST_DEFAULT 4 375 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 376 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 377 378 #define ALE_TX_JUMBO_THRESH 0x1584 379 #define TX_JUMBO_THRESH_MASK 0x000007FF 380 #define TX_JUMBO_THRESH_SHIFT 0 381 #define TX_JUMBO_THRESH_UNIT 8 382 #define TX_JUMBO_THRESH_UNIT_SHIFT 3 383 384 #define ALE_RXQ_CFG 0x15A0 385 #define RXQ_CFG_ALIGN_32 0x00000000 386 #define RXQ_CFG_ALIGN_64 0x00000001 387 #define RXQ_CFG_ALIGN_128 0x00000002 388 #define RXQ_CFG_ALIGN_256 0x00000003 389 #define RXQ_CFG_QUEUE1_ENB 0x00000010 390 #define RXQ_CFG_QUEUE2_ENB 0x00000020 391 #define RXQ_CFG_QUEUE3_ENB 0x00000040 392 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 393 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 394 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 395 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 396 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 397 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 398 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 399 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 400 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 401 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 402 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 403 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 404 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 405 #define RXQ_CFG_ENB 0x80000000 406 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 407 408 #define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ 409 #define RX_JUMBO_THRESH_MASK 0x07FF 410 #define RX_JUMBO_LKAH_MASK 0x7800 411 #define RX_JUMBO_THRESH_MASK_SHIFT 0 412 #define RX_JUMBO_THRESH_UNIT 8 413 #define RX_JUMBO_THRESH_UNIT_SHIFT 3 414 #define RX_JUMBO_LKAH_SHIFT 11 415 #define RX_JUMBO_LKAH_DEFAULT 1 416 417 #define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 418 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 419 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 420 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 421 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 422 423 #define ALE_CMB_RXF1 0x15B4 424 425 #define ALE_CMB_RXF2 0x15B8 426 427 #define ALE_CMB_RXF3 0x15BC 428 429 #define ALE_DMA_CFG 0x15C0 430 #define DMA_CFG_IN_ORDER 0x00000001 431 #define DMA_CFG_ENH_ORDER 0x00000002 432 #define DMA_CFG_OUT_ORDER 0x00000004 433 #define DMA_CFG_RCB_64 0x00000000 434 #define DMA_CFG_RCB_128 0x00000008 435 #define DMA_CFG_RD_BURST_128 0x00000000 436 #define DMA_CFG_RD_BURST_256 0x00000010 437 #define DMA_CFG_RD_BURST_512 0x00000020 438 #define DMA_CFG_RD_BURST_1024 0x00000030 439 #define DMA_CFG_RD_BURST_2048 0x00000040 440 #define DMA_CFG_RD_BURST_4096 0x00000050 441 #define DMA_CFG_WR_BURST_128 0x00000000 442 #define DMA_CFG_WR_BURST_256 0x00000080 443 #define DMA_CFG_WR_BURST_512 0x00000100 444 #define DMA_CFG_WR_BURST_1024 0x00000180 445 #define DMA_CFG_WR_BURST_2048 0x00000200 446 #define DMA_CFG_WR_BURST_4096 0x00000280 447 #define DMA_CFG_RD_REQ_PRI 0x00000400 448 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 449 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 450 #define DMA_CFG_TXCMB_ENB 0x00100000 451 #define DMA_CFG_RXCMB_ENB 0x00200000 452 #define DMA_CFG_RD_BURST_MASK 0x07 453 #define DMA_CFG_RD_BURST_SHIFT 4 454 #define DMA_CFG_WR_BURST_MASK 0x07 455 #define DMA_CFG_WR_BURST_SHIFT 7 456 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 457 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 458 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 459 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 460 461 #define ALE_SMB_STAT_TIMER 0x15C4 462 463 #define ALE_INT_TRIG_THRESH 0x15C8 464 #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF 465 #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 466 #define INT_TRIG_TX_THRESH_SHIFT 0 467 #define INT_TRIG_RX_THRESH_SHIFT 16 468 469 #define ALE_INT_TRIG_TIMER 0x15CC 470 #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF 471 #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF 472 #define INT_TRIG_TX_TIMER_SHIFT 0 473 #define INT_TRIG_RX_TIMER_SHIFT 16 474 475 #define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 476 477 #define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 478 479 #define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 480 481 #define ALE_RXF2_PAGE1_ADDR_LO 0x15DC 482 483 #define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 484 485 #define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 486 487 #define ALE_MBOX_TPD_PROD_IDX 0x15F0 488 489 #define ALE_RXF0_PAGE0 0x15F4 490 491 #define ALE_RXF0_PAGE1 0x15F5 492 493 #define ALE_RXF1_PAGE0 0x15F6 494 495 #define ALE_RXF1_PAGE1 0x15F7 496 497 #define ALE_RXF2_PAGE0 0x15F8 498 499 #define ALE_RXF2_PAGE1 0x15F9 500 501 #define ALE_RXF3_PAGE0 0x15FA 502 503 #define ALE_RXF3_PAGE1 0x15FB 504 505 #define RXF_VALID 0x01 506 507 #define ALE_INTR_STATUS 0x1600 508 #define INTR_SMB 0x00000001 509 #define INTR_TIMER 0x00000002 510 #define INTR_MANUAL_TIMER 0x00000004 511 #define INTR_RX_FIFO_OFLOW 0x00000008 512 #define INTR_RXF0_OFLOW 0x00000010 513 #define INTR_RXF1_OFLOW 0x00000020 514 #define INTR_RXF2_OFLOW 0x00000040 515 #define INTR_RXF3_OFLOW 0x00000080 516 #define INTR_TX_FIFO_UNDERRUN 0x00000100 517 #define INTR_RX0_PAGE_FULL 0x00000200 518 #define INTR_DMA_RD_TO_RST 0x00000400 519 #define INTR_DMA_WR_TO_RST 0x00000800 520 #define INTR_GPHY 0x00001000 521 #define INTR_TX_CREDIT 0x00002000 522 #define INTR_GPHY_LOW_PW 0x00004000 523 #define INTR_RX_PKT 0x00010000 524 #define INTR_TX_PKT 0x00020000 525 #define INTR_TX_DMA 0x00040000 526 #define INTR_RX_PKT1 0x00080000 527 #define INTR_RX_PKT2 0x00100000 528 #define INTR_RX_PKT3 0x00200000 529 #define INTR_MAC_RX 0x00400000 530 #define INTR_MAC_TX 0x00800000 531 #define INTR_UNDERRUN 0x01000000 532 #define INTR_FRAME_ERROR 0x02000000 533 #define INTR_FRAME_OK 0x04000000 534 #define INTR_CSUM_ERROR 0x08000000 535 #define INTR_PHY_LINK_DOWN 0x10000000 536 #define INTR_DIS_INT 0x80000000 537 538 /* Interrupt Mask Register */ 539 #define ALE_INTR_MASK 0x1604 540 541 #define ALE_INTRS \ 542 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 543 INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ 544 INTR_TX_FIFO_UNDERRUN) 545 546 /* 547 * AR81xx requires register access to get MAC statistics 548 * and the format of statistics seems to be the same of L1 . 549 */ 550 #define ALE_RX_MIB_BASE 0x1700 551 552 #define ALE_TX_MIB_BASE 0x1760 553 554 /* Statistics counters collected by the MAC. */ 555 struct smb { 556 /* Rx stats. */ 557 uint32_t rx_frames; 558 uint32_t rx_bcast_frames; 559 uint32_t rx_mcast_frames; 560 uint32_t rx_pause_frames; 561 uint32_t rx_control_frames; 562 uint32_t rx_crcerrs; 563 uint32_t rx_lenerrs; 564 uint32_t rx_bytes; 565 uint32_t rx_runts; 566 uint32_t rx_fragments; 567 uint32_t rx_pkts_64; 568 uint32_t rx_pkts_65_127; 569 uint32_t rx_pkts_128_255; 570 uint32_t rx_pkts_256_511; 571 uint32_t rx_pkts_512_1023; 572 uint32_t rx_pkts_1024_1518; 573 uint32_t rx_pkts_1519_max; 574 uint32_t rx_pkts_truncated; 575 uint32_t rx_fifo_oflows; 576 uint32_t rx_rrs_errs; 577 uint32_t rx_alignerrs; 578 uint32_t rx_bcast_bytes; 579 uint32_t rx_mcast_bytes; 580 uint32_t rx_pkts_filtered; 581 /* Tx stats. */ 582 uint32_t tx_frames; 583 uint32_t tx_bcast_frames; 584 uint32_t tx_mcast_frames; 585 uint32_t tx_pause_frames; 586 uint32_t tx_excess_defer; 587 uint32_t tx_control_frames; 588 uint32_t tx_deferred; 589 uint32_t tx_bytes; 590 uint32_t tx_pkts_64; 591 uint32_t tx_pkts_65_127; 592 uint32_t tx_pkts_128_255; 593 uint32_t tx_pkts_256_511; 594 uint32_t tx_pkts_512_1023; 595 uint32_t tx_pkts_1024_1518; 596 uint32_t tx_pkts_1519_max; 597 uint32_t tx_single_colls; 598 uint32_t tx_multi_colls; 599 uint32_t tx_late_colls; 600 uint32_t tx_excess_colls; 601 uint32_t tx_underrun; 602 uint32_t tx_desc_underrun; 603 uint32_t tx_lenerrs; 604 uint32_t tx_pkts_truncated; 605 uint32_t tx_bcast_bytes; 606 uint32_t tx_mcast_bytes; 607 } __packed; 608 609 #define ALE_HOST_RXF0_PAGEOFF 0x1800 610 611 #define ALE_TPD_CONS_IDX 0x1804 612 613 #define ALE_HOST_RXF1_PAGEOFF 0x1808 614 615 #define ALE_HOST_RXF2_PAGEOFF 0x180C 616 617 #define ALE_HOST_RXF3_PAGEOFF 0x1810 618 619 #define ALE_RXF0_CMB0_ADDR_LO 0x1820 620 621 #define ALE_RXF0_CMB1_ADDR_LO 0x1824 622 623 #define ALE_RXF1_CMB0_ADDR_LO 0x1828 624 625 #define ALE_RXF1_CMB1_ADDR_LO 0x182C 626 627 #define ALE_RXF2_CMB0_ADDR_LO 0x1830 628 629 #define ALE_RXF2_CMB1_ADDR_LO 0x1834 630 631 #define ALE_RXF3_CMB0_ADDR_LO 0x1838 632 633 #define ALE_RXF3_CMB1_ADDR_LO 0x183C 634 635 #define ALE_TX_CMB_ADDR_LO 0x1840 636 637 #define ALE_SMB_ADDR_LO 0x1844 638 639 /* 640 * RRS(receive return status) structure. 641 * 642 * Note: 643 * Atheros AR81xx does not support descriptor based DMA on Rx 644 * instead it just prepends a Rx status structure prior to a 645 * received frame which also resides on the same Rx buffer. 646 * This means driver should copy an entire frame from the 647 * buffer to new mbuf chain which in turn greatly increases CPU 648 * cycles and effectively nullify the advantage of DMA 649 * operation of controller. So you should have fast CPU to cope 650 * with the copy operation. Implementing flow-controls may help 651 * a lot to minimize Rx FIFO overflows but it's not available 652 * yet on FreeBSD and hardware doesn't seem to support 653 * fine-grained Tx/Rx flow controls. 654 */ 655 struct rx_rs { 656 uint32_t seqno; 657 #define ALE_RD_SEQNO_MASK 0x0000FFFF 658 #define ALE_RD_HASH_MASK 0xFFFF0000 659 #define ALE_RD_SEQNO_SHIFT 0 660 #define ALE_RD_HASH_SHIFT 16 661 #define ALE_RX_SEQNO(x) \ 662 (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) 663 uint32_t length; 664 #define ALE_RD_CSUM_MASK 0x0000FFFF 665 #define ALE_RD_LEN_MASK 0x3FFF0000 666 #define ALE_RD_CPU_MASK 0xC0000000 667 #define ALE_RD_CSUM_SHIFT 0 668 #define ALE_RD_LEN_SHIFT 16 669 #define ALE_RD_CPU_SHIFT 30 670 #define ALE_RX_CSUM(x) \ 671 (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) 672 #define ALE_RX_BYTES(x) \ 673 (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) 674 #define ALE_RX_CPU(x) \ 675 (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) 676 uint32_t flags; 677 #define ALE_RD_RSS_IPV4 0x00000001 678 #define ALE_RD_RSS_IPV4_TCP 0x00000002 679 #define ALE_RD_RSS_IPV6 0x00000004 680 #define ALE_RD_RSS_IPV6_TCP 0x00000008 681 #define ALE_RD_IPV6 0x00000010 682 #define ALE_RD_IPV4_FRAG 0x00000020 683 #define ALE_RD_IPV4_DF 0x00000040 684 #define ALE_RD_802_3 0x00000080 685 #define ALE_RD_VLAN 0x00000100 686 #define ALE_RD_ERROR 0x00000200 687 #define ALE_RD_IPV4 0x00000400 688 #define ALE_RD_UDP 0x00000800 689 #define ALE_RD_TCP 0x00001000 690 #define ALE_RD_BCAST 0x00002000 691 #define ALE_RD_MCAST 0x00004000 692 #define ALE_RD_PAUSE 0x00008000 693 #define ALE_RD_CRC 0x00010000 694 #define ALE_RD_CODE 0x00020000 695 #define ALE_RD_DRIBBLE 0x00040000 696 #define ALE_RD_RUNT 0x00080000 697 #define ALE_RD_OFLOW 0x00100000 698 #define ALE_RD_TRUNC 0x00200000 699 #define ALE_RD_IPCSUM_NOK 0x00400000 700 #define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 701 #define ALE_RD_LENGTH_NOK 0x01000000 702 #define ALE_RD_DES_ADDR_FILTERED 0x02000000 703 uint32_t vtags; 704 #define ALE_RD_HASH_HI_MASK 0x0000FFFF 705 #define ALE_RD_HASH_HI_SHIFT 0 706 #define ALE_RD_VLAN_MASK 0xFFFF0000 707 #define ALE_RD_VLAN_SHIFT 16 708 #define ALE_RX_VLAN(x) \ 709 (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) 710 #define ALE_RX_VLAN_TAG(x) \ 711 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 712 } __packed; 713 714 /* Tx descriptor. */ 715 struct tx_desc { 716 uint64_t addr; 717 uint32_t len; 718 #define ALE_TD_VLAN_MASK 0xFFFF0000 719 #define ALE_TD_PKT_INT 0x00008000 720 #define ALE_TD_DMA_INT 0x00004000 721 #define ALE_TD_BUFLEN_MASK 0x00003FFF 722 #define ALE_TD_VLAN_SHIFT 16 723 #define ALE_TX_VLAN_TAG(x) \ 724 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 725 #define ALE_TD_BUFLEN_SHIFT 0 726 #define ALE_TX_BYTES(x) \ 727 (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) 728 uint32_t flags; 729 #define ALE_TD_MSS 0xFFF80000 730 #define ALE_TD_TSO_HDR 0x00040000 731 #define ALE_TD_TCPHDR_LEN 0x0003C000 732 #define ALE_TD_IPHDR_LEN 0x00003C00 733 #define ALE_TD_IPV6HDR_LEN2 0x00003C00 734 #define ALE_TD_LLC_SNAP 0x00000200 735 #define ALE_TD_VLAN_TAGGED 0x00000100 736 #define ALE_TD_UDPCSUM 0x00000080 737 #define ALE_TD_TCPCSUM 0x00000040 738 #define ALE_TD_IPCSUM 0x00000020 739 #define ALE_TD_IPV6HDR_LEN1 0x000000E0 740 #define ALE_TD_TSO 0x00000010 741 #define ALE_TD_CXSUM 0x00000008 742 #define ALE_TD_INSERT_VLAN_TAG 0x00000004 743 #define ALE_TD_IPV6 0x00000002 744 #define ALE_TD_EOP 0x00000001 745 746 #define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 747 #define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 748 #define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 749 #define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 750 #define ALE_TD_MSS_SHIFT 19 751 #define ALE_TD_TCPHDR_LEN_SHIFT 14 752 #define ALE_TD_IPHDR_LEN_SHIFT 10 753 } __packed; 754 755 #define ALE_TX_RING_CNT 256 /* Should be multiple of 4. */ 756 #define ALE_TX_RING_CNT_MIN 32 757 #define ALE_TX_RING_CNT_MAX 1020 758 #define ALE_TX_RING_ALIGN 8 759 #define ALE_RX_PAGE_ALIGN 32 760 #define ALE_RX_PAGES 2 761 #define ALE_CMB_ALIGN 32 762 763 #define ALE_TSO_MAXSEGSIZE 4096 764 #define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 765 #define ALE_MAXTXSEGS 32 766 767 #define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 768 #define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32) 769 770 /* Water mark to kick reclaiming Tx buffers. */ 771 #define ALE_TX_DESC_HIWAT (ALE_TX_RING_CNT - ((ALE_TX_RING_CNT * 4) / 10)) 772 773 #define ALE_MSI_MESSAGES 1 774 #define ALE_MSIX_MESSAGES 1 775 776 /* 777 * TODO : Should get real jumbo MTU size. 778 * The hardware seems to have trouble in dealing with large 779 * frame length. If you encounter instability issue, use 780 * lower MTU size. 781 */ 782 #define ALE_JUMBO_FRAMELEN 8132 783 #define ALE_JUMBO_MTU \ 784 (ALE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) 785 #define ALE_MAX_FRAMELEN (ETHER_MAX_LEN + EVL_ENCAPLEN) 786 787 #define ALE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 788 789 struct ale_txdesc { 790 struct mbuf *tx_m; 791 bus_dmamap_t tx_dmamap; 792 }; 793 794 struct ale_rx_page { 795 bus_dmamap_t page_map; 796 bus_dma_segment_t page_seg; 797 uint8_t *page_addr; 798 bus_addr_t page_paddr; 799 bus_dmamap_t cmb_map; 800 bus_dma_segment_t cmb_seg; 801 uint32_t *cmb_addr; 802 bus_addr_t cmb_paddr; 803 uint32_t cons; 804 }; 805 806 struct ale_chain_data{ 807 struct ale_txdesc ale_txdesc[ALE_TX_RING_CNT]; 808 bus_dmamap_t ale_tx_ring_map; 809 bus_dma_segment_t ale_tx_ring_seg; 810 bus_dmamap_t ale_rx_mblock_map[ALE_RX_PAGES]; 811 bus_dma_segment_t ale_rx_mblock_seg[ALE_RX_PAGES]; 812 struct tx_desc *ale_tx_ring; 813 bus_addr_t ale_tx_ring_paddr; 814 uint32_t *ale_tx_cmb; 815 bus_addr_t ale_tx_cmb_paddr; 816 bus_dmamap_t ale_tx_cmb_map; 817 bus_dma_segment_t ale_tx_cmb_seg; 818 819 uint32_t ale_tx_prod; 820 uint32_t ale_tx_cons; 821 int ale_tx_cnt; 822 struct ale_rx_page ale_rx_page[ALE_RX_PAGES]; 823 int ale_rx_curp; 824 uint16_t ale_rx_seqno; 825 }; 826 827 #define ALE_TX_RING_SZ \ 828 (sizeof(struct tx_desc) * ALE_TX_RING_CNT) 829 #define ALE_RX_PAGE_SZ_MIN (8 * 1024) 830 #define ALE_RX_PAGE_SZ_MAX (1024 * 1024) 831 #define ALE_RX_FRAMES_PAGE 128 832 #define ALE_RX_PAGE_SZ \ 833 (roundup(ALE_MAX_FRAMELEN, ALE_RX_PAGE_ALIGN) * ALE_RX_FRAMES_PAGE) 834 #define ALE_TX_CMB_SZ (sizeof(uint32_t)) 835 #define ALE_RX_CMB_SZ (sizeof(uint32_t)) 836 837 #define ALE_PROC_MIN (ALE_RX_FRAMES_PAGE / 4) 838 #define ALE_PROC_MAX \ 839 ((ALE_RX_PAGE_SZ * ALE_RX_PAGES) / ETHER_MAX_LEN) 840 #define ALE_PROC_DEFAULT (ALE_PROC_MAX / 4) 841 842 struct ale_hw_stats { 843 /* Rx stats. */ 844 uint32_t rx_frames; 845 uint32_t rx_bcast_frames; 846 uint32_t rx_mcast_frames; 847 uint32_t rx_pause_frames; 848 uint32_t rx_control_frames; 849 uint32_t rx_crcerrs; 850 uint32_t rx_lenerrs; 851 uint64_t rx_bytes; 852 uint32_t rx_runts; 853 uint32_t rx_fragments; 854 uint32_t rx_pkts_64; 855 uint32_t rx_pkts_65_127; 856 uint32_t rx_pkts_128_255; 857 uint32_t rx_pkts_256_511; 858 uint32_t rx_pkts_512_1023; 859 uint32_t rx_pkts_1024_1518; 860 uint32_t rx_pkts_1519_max; 861 uint32_t rx_pkts_truncated; 862 uint32_t rx_fifo_oflows; 863 uint32_t rx_rrs_errs; 864 uint32_t rx_alignerrs; 865 uint64_t rx_bcast_bytes; 866 uint64_t rx_mcast_bytes; 867 uint32_t rx_pkts_filtered; 868 /* Tx stats. */ 869 uint32_t tx_frames; 870 uint32_t tx_bcast_frames; 871 uint32_t tx_mcast_frames; 872 uint32_t tx_pause_frames; 873 uint32_t tx_excess_defer; 874 uint32_t tx_control_frames; 875 uint32_t tx_deferred; 876 uint64_t tx_bytes; 877 uint32_t tx_pkts_64; 878 uint32_t tx_pkts_65_127; 879 uint32_t tx_pkts_128_255; 880 uint32_t tx_pkts_256_511; 881 uint32_t tx_pkts_512_1023; 882 uint32_t tx_pkts_1024_1518; 883 uint32_t tx_pkts_1519_max; 884 uint32_t tx_single_colls; 885 uint32_t tx_multi_colls; 886 uint32_t tx_late_colls; 887 uint32_t tx_excess_colls; 888 uint32_t tx_underrun; 889 uint32_t tx_desc_underrun; 890 uint32_t tx_lenerrs; 891 uint32_t tx_pkts_truncated; 892 uint64_t tx_bcast_bytes; 893 uint64_t tx_mcast_bytes; 894 /* Misc. */ 895 uint32_t reset_brk_seq; 896 }; 897 898 /* 899 * Software state per device. 900 */ 901 struct ale_softc { 902 struct device sc_dev; 903 struct arpcom sc_arpcom; 904 905 bus_space_tag_t sc_mem_bt; 906 bus_space_handle_t sc_mem_bh; 907 bus_size_t sc_mem_size; 908 bus_dma_tag_t sc_dmat; 909 pci_chipset_tag_t sc_pct; 910 pcitag_t sc_pcitag; 911 912 void *sc_irq_handle; 913 914 struct mii_data sc_miibus; 915 int ale_phyaddr; 916 917 int ale_rev; 918 int ale_chip_rev; 919 uint8_t ale_eaddr[ETHER_ADDR_LEN]; 920 uint32_t ale_dma_rd_burst; 921 uint32_t ale_dma_wr_burst; 922 int ale_flags; 923 #define ALE_FLAG_PCIE 0x0001 924 #define ALE_FLAG_PCIX 0x0002 925 #define ALE_FLAG_MSI 0x0004 926 #define ALE_FLAG_MSIX 0x0008 927 #define ALE_FLAG_PMCAP 0x0010 928 #define ALE_FLAG_FASTETHER 0x0020 929 #define ALE_FLAG_JUMBO 0x0040 930 #define ALE_FLAG_RXCSUM_BUG 0x0080 931 #define ALE_FLAG_TXCSUM_BUG 0x0100 932 #define ALE_FLAG_TXCMB_BUG 0x0200 933 #define ALE_FLAG_DETACH 0x4000 934 #define ALE_FLAG_LINK 0x8000 935 936 struct timeout ale_tick_ch; 937 struct ale_hw_stats ale_stats; 938 struct ale_chain_data ale_cdata; 939 int ale_int_rx_mod; 940 int ale_int_tx_mod; 941 int ale_max_frame_size; 942 int ale_pagesize; 943 944 }; 945 946 /* Register access macros. */ 947 #define CSR_WRITE_4(_sc, reg, val) \ 948 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 949 #define CSR_WRITE_2(_sc, reg, val) \ 950 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 951 #define CSR_WRITE_1(_sc, reg, val) \ 952 bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 953 #define CSR_READ_2(_sc, reg) \ 954 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 955 #define CSR_READ_4(_sc, reg) \ 956 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 957 958 #define ALE_TX_TIMEOUT 5 959 #define ALE_RESET_TIMEOUT 100 960 #define ALE_TIMEOUT 1000 961 #define ALE_PHY_TIMEOUT 1000 962 963 #endif /* _IF_ALEREG_H */ 964