1 /* $OpenBSD: anxdp.c,v 1.7 2023/01/01 01:34:33 jsg Exp $ */
2 /* $NetBSD: anx_dp.c,v 1.2 2020/01/04 12:08:32 jmcneill Exp $ */
3 /*-
4 * Copyright (c) 2019 Jonathan A. Kollasch <jakllsch@kollasch.net>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/device.h>
31 #include <sys/systm.h>
32
33 #include <machine/bus.h>
34
35 #include <dev/ic/anxdp.h>
36
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_crtc_helper.h>
41 #include <drm/display/drm_dp_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <drm/drm_edid.h>
44
45 #define ANXDP_DP_TX_VERSION 0x010
46 #define ANXDP_TX_SW_RESET 0x014
47 #define RESET_DP_TX (1 << 0)
48 #define ANXDP_FUNC_EN_1 0x018
49 #define MASTER_VID_FUNC_EN_N (1 << 7)
50 #define RK_VID_CAP_FUNC_EN_N (1 << 6)
51 #define SLAVE_VID_FUNC_EN_N (1 << 5)
52 #define RK_VID_FIFO_FUNC_EN_N (1 << 5)
53 #define AUD_FIFO_FUNC_EN_N (1 << 4)
54 #define AUD_FUNC_EN_N (1 << 3)
55 #define HDCP_FUNC_EN_N (1 << 2)
56 #define CRC_FUNC_EN_N (1 << 1)
57 #define SW_FUNC_EN_N (1 << 0)
58 #define ANXDP_FUNC_EN_2 0x01c
59 #define SSC_FUNC_EN_N (1 << 7)
60 #define AUX_FUNC_EN_N (1 << 2)
61 #define SERDES_FIFO_FUNC_EN_N (1 << 1)
62 #define LS_CLK_DOMAIN_FUNC_EN_N (1 << 0)
63 #define ANXDP_VIDEO_CTL_1 0x020
64 #define VIDEO_EN (1 << 7)
65 #define VIDEO_MUTE (1 << 6)
66 #define ANXDP_VIDEO_CTL_2 0x024
67 #define ANXDP_VIDEO_CTL_3 0x028
68 #define ANXDP_VIDEO_CTL_4 0x02c
69 #define ANXDP_VIDEO_CTL_8 0x03c
70 #define ANXDP_VIDEO_CTL_10 0x044
71 #define F_SEL (1 << 4)
72 #define SLAVE_I_SCAN_CFG (1 << 2)
73 #define SLAVE_VSYNC_P_CFG (1 << 1)
74 #define SLAVE_HSYNC_P_CFG (1 << 0)
75 #define ANXDP_PLL_REG_1 0x0fc
76 #define REF_CLK_24M (1 << 0)
77 #define RKANXDP_PD 0x12c
78 #define DP_INC_BG (1 << 7)
79 #define DP_EXP_PD (1 << 6)
80 #define DP_PHY_PD (1 << 5)
81 #define RK_AUX_PD (1 << 5)
82 #define AUX_PD (1 << 4)
83 #define RK_PLL_PD (1 << 4)
84 #define CHx_PD(x) (1 << x) /* 0<=x<=3 */
85 #define DP_ALL_PD 0xff
86 #define ANXDP_LANE_MAP 0x35c
87 #define ANXDP_ANALOG_CTL_1 0x370
88 #define TX_TERMINAL_CTRL_50_OHM (1 << 4)
89 #define ANXDP_ANALOG_CTL_2 0x374
90 #define SEL_24M (1 << 3)
91 #define TX_DVDD_BIT_1_0625V 0x4
92 #define ANXDP_ANALOG_CTL_3 0x378
93 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
94 #define VCO_BIT_600_MICRO (0x5 << 0)
95 #define ANXDP_PLL_FILTER_CTL_1 0x37c
96 #define PD_RING_OSC (1 << 6)
97 #define AUX_TERMINAL_CTRL_50_OHM (2 << 4)
98 #define TX_CUR1_2X (1 << 2)
99 #define TX_CUR_16_MA 3
100 #define ANXDP_TX_AMP_TUNING_CTL 0x380
101 #define ANXDP_AUX_HW_RETRY_CTL 0x390
102 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) ((x) << 8)
103 #define AUX_HW_RETRY_INTERVAL_600_US (0 << 3)
104 #define AUX_HW_RETRY_INTERVAL_800_US (1 << 3)
105 #define AUX_HW_RETRY_INTERVAL_1000_US (2 << 3)
106 #define AUX_HW_RETRY_INTERVAL_1800_US (3 << 3)
107 #define AUX_HW_RETRY_COUNT_SEL(x) ((x) << 0)
108 #define ANXDP_COMMON_INT_STA_1 0x3c4
109 #define PLL_LOCK_CHG (1 << 6)
110 #define ANXDP_COMMON_INT_STA_2 0x3c8
111 #define ANXDP_COMMON_INT_STA_3 0x3cc
112 #define ANXDP_COMMON_INT_STA_4 0x3d0
113 #define ANXDP_DP_INT_STA 0x3dc
114 #define INT_HPD (1 << 6)
115 #define HW_TRAINING_FINISH (1 << 5)
116 #define RPLY_RECEIV (1 << 1)
117 #define AUX_ERR (1 << 0)
118 #define ANXDP_SYS_CTL_1 0x600
119 #define DET_STA (1 << 2)
120 #define FORCE_DET (1 << 1)
121 #define DET_CTRL (1 << 0)
122 #define ANXDP_SYS_CTL_2 0x604
123 #define ANXDP_SYS_CTL_3 0x608
124 #define HPD_STATUS (1 << 6)
125 #define F_HPD (1 << 5)
126 #define HPD_CTRL (1 << 4)
127 #define HDCP_RDY (1 << 3)
128 #define STRM_VALID (1 << 2)
129 #define F_VALID (1 << 1)
130 #define VALID_CTRL (1 << 0)
131 #define ANXDP_SYS_CTL_4 0x60c
132 #define ANXDP_PKT_SEND_CTL 0x640
133 #define ANXDP_HDCP_CTL 0x648
134 #define ANXDP_LINK_BW_SET 0x680
135 #define ANXDP_LANE_COUNT_SET 0x684
136 #define ANXDP_TRAINING_PTN_SET 0x688
137 #define SCRAMBLING_DISABLE (1 << 5)
138 #define SW_TRAINING_PATTERN_SET_PTN2 (2 << 0)
139 #define SW_TRAINING_PATTERN_SET_PTN1 (1 << 0)
140 #define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */
141 #define MAX_PRE_REACH (1 << 5)
142 #define PRE_EMPHASIS_SET(x) ((x) << 3)
143 #define MAX_DRIVE_REACH (1 << 2)
144 #define DRIVE_CURRENT_SET(x) ((x) << 0)
145 #define ANXDP_DEBUG_CTL 0x6c0
146 #define PLL_LOCK (1 << 4)
147 #define F_PLL_LOCK (1 << 3)
148 #define PLL_LOCK_CTRL (1 << 2)
149 #define PN_INV (1 << 0)
150 #define ANXDP_LINK_DEBUG_CTL 0x6e0
151 #define ANXDP_PLL_CTL 0x71c
152 #define ANXDP_PHY_PD 0x720
153 #define ANXDP_PHY_TEST 0x724
154 #define MACRO_RST (1 << 5)
155 #define ANXDP_M_AUD_GEN_FILTER_TH 0x778
156 #define ANXDP_AUX_CH_STA 0x780
157 #define AUX_BUSY (1 << 4)
158 #define AUX_STATUS(x) (((x) >> 0) & 0xf)
159 #define ANXDP_AUX_ERR_NUM 0x784
160 #define ANXDP_AUX_CH_DEFER_CTL 0x788
161 #define DEFER_CTRL_EN (1 << 7)
162 #define DEFER_COUNT(x) ((x) << 0)
163 #define ANXDP_AUX_RX_COMM 0x78c
164 #define AUX_RX_COMM_I2C_DEFER (1 << 3)
165 #define AUX_RX_COMM_AUX_DEFER (1 << 1)
166 #define ANXDP_BUFFER_DATA_CTL 0x790
167 #define BUF_CLR (1 << 7)
168 #define BUF_DATA_COUNT(x) ((x) << 0)
169 #define ANXDP_AUX_CH_CTL_1 0x794
170 #define AUX_LENGTH(x) (((x) - 1) << 4)
171 #define AUX_TX_COMM(x) (((x) >> 0) & 0xf)
172 #define AUX_TX_COMM_DP (1 << 3)
173 #define AUX_TX_COMM_MOT (1 << 2)
174 #define AUX_TX_COMM_READ (1 << 0)
175 #define ANXDP_AUX_ADDR_7_0 0x798
176 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
177 #define ANXDP_AUX_ADDR_15_8 0x79c
178 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
179 #define ANXDP_AUX_ADDR_19_16 0x7a0
180 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf)
181 #define ANXDP_AUX_CH_CTL_2 0x7a4
182 #define ADDR_ONLY (1 << 1)
183 #define AUX_EN (1 << 0)
184 #define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x))
185 #define ANXDP_SOC_GENERAL_CTL 0x800
186 #define AUDIO_MODE_SPDIF_MODE (1 << 8)
187 #define VIDEO_MODE_SLAVE_MODE (1 << 1)
188 #define ANXDP_CRC_CON 0x890
189 #define ANXDP_PLL_REG_2 0x9e4
190 #define ANXDP_PLL_REG_3 0x9e8
191 #define ANXDP_PLL_REG_4 0x9ec
192 #define ANXDP_PLL_REG_5 0xa00
193
194 static inline const bool
isrockchip(struct anxdp_softc * sc)195 isrockchip(struct anxdp_softc *sc)
196 {
197 return (sc->sc_flags & ANXDP_FLAG_ROCKCHIP) != 0;
198 }
199
200 enum drm_connector_status
anxdp_connector_detect(struct drm_connector * connector,bool force)201 anxdp_connector_detect(struct drm_connector *connector, bool force)
202 {
203 #if 0
204 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector);
205 struct anxdp_softc *sc = anxdp_connector->sc;
206
207 /* XXX HPD */
208 #endif
209 return connector_status_connected;
210 }
211
212 void
anxdp_connector_destroy(struct drm_connector * connector)213 anxdp_connector_destroy(struct drm_connector *connector)
214 {
215 drm_connector_unregister(connector);
216 drm_connector_cleanup(connector);
217 }
218
219 struct drm_connector_funcs anxdp_connector_funcs = {
220 .dpms = drm_helper_connector_dpms,
221 .detect = anxdp_connector_detect,
222 .fill_modes = drm_helper_probe_single_connector_modes,
223 .destroy = anxdp_connector_destroy,
224 .reset = drm_atomic_helper_connector_reset,
225 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
226 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
227 };
228
229 void
anxdp_analog_power_up_all(struct anxdp_softc * sc)230 anxdp_analog_power_up_all(struct anxdp_softc *sc)
231 {
232 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD;
233
234 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, DP_ALL_PD);
235 delay(15);
236 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg,
237 DP_ALL_PD & ~DP_INC_BG);
238 delay(15);
239 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, 0);
240 }
241
242 int
anxdp_await_pll_lock(struct anxdp_softc * sc)243 anxdp_await_pll_lock(struct anxdp_softc *sc)
244 {
245 u_int timeout;
246
247 for (timeout = 0; timeout < 100; timeout++) {
248 if ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL) &
249 PLL_LOCK) != 0)
250 return 0;
251 delay(20);
252 }
253
254 return ETIMEDOUT;
255 }
256
257 void
anxdp_init_hpd(struct anxdp_softc * sc)258 anxdp_init_hpd(struct anxdp_softc *sc)
259 {
260 uint32_t sc3;
261
262 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_4, 0x7);
263 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA, INT_HPD);
264
265 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3);
266 sc3 &= ~(F_HPD | HPD_CTRL);
267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3);
268
269 sc3 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3);
270 sc3 |= F_HPD | HPD_CTRL;
271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SYS_CTL_3, sc3);
272 }
273
274 void
anxdp_init_aux(struct anxdp_softc * sc)275 anxdp_init_aux(struct anxdp_softc *sc)
276 {
277 uint32_t fe2, pd, hrc;
278 const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD;
279 const uint32_t pd_mask = isrockchip(sc) ? RK_AUX_PD : AUX_PD;
280
281 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA,
282 RPLY_RECEIV | AUX_ERR);
283
284 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg);
285 pd |= pd_mask;
286 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd);
287
288 delay(11);
289
290 pd = bus_space_read_4(sc->sc_iot, sc->sc_ioh, pd_reg);
291 pd &= ~pd_mask;
292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, pd_reg, pd);
293
294 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2);
295 fe2 |= AUX_FUNC_EN_N;
296 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2);
297
298 hrc = AUX_HW_RETRY_COUNT_SEL(0) | AUX_HW_RETRY_INTERVAL_600_US;
299 if (!isrockchip(sc))
300 hrc |= AUX_BIT_PERIOD_EXPECTED_DELAY(3);
301 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_HW_RETRY_CTL, hrc);
302
303 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_DEFER_CTL,
304 DEFER_CTRL_EN | DEFER_COUNT(1));
305
306 fe2 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2);
307 fe2 &= ~AUX_FUNC_EN_N;
308 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, fe2);
309 }
310
311 int
anxdp_connector_get_modes(struct drm_connector * connector)312 anxdp_connector_get_modes(struct drm_connector *connector)
313 {
314 struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector);
315 struct anxdp_softc *sc = anxdp_connector->sc;
316 struct edid *pedid = NULL;
317 int error;
318
319 if (sc->sc_panel)
320 return drm_panel_get_modes(sc->sc_panel, connector);
321
322 pedid = drm_get_edid(connector, &sc->sc_dpaux.ddc);
323
324 drm_connector_update_edid_property(connector, pedid);
325 if (pedid == NULL)
326 return 0;
327
328 error = drm_add_edid_modes(connector, pedid);
329
330 if (pedid != NULL)
331 kfree(pedid);
332
333 return error;
334 }
335
336 struct drm_connector_helper_funcs anxdp_connector_helper_funcs = {
337 .get_modes = anxdp_connector_get_modes,
338 };
339
340 int
anxdp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)341 anxdp_bridge_attach(struct drm_bridge *bridge,
342 enum drm_bridge_attach_flags flags)
343 {
344 struct anxdp_softc *sc = bridge->driver_private;
345 struct anxdp_connector *anxdp_connector = &sc->sc_connector;
346 struct drm_connector *connector = &anxdp_connector->base;
347 int error;
348
349 anxdp_connector->sc = sc;
350
351 connector->polled =
352 DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
353 connector->interlace_allowed = 0;
354 connector->doublescan_allowed = 0;
355
356 drm_connector_init(bridge->dev, connector, &anxdp_connector_funcs,
357 connector->connector_type);
358 drm_connector_helper_add(connector, &anxdp_connector_helper_funcs);
359
360 error = drm_connector_attach_encoder(connector, bridge->encoder);
361 if (error != 0)
362 return error;
363
364 return drm_connector_register(connector);
365 }
366
367 void
anxdp_macro_reset(struct anxdp_softc * sc)368 anxdp_macro_reset(struct anxdp_softc *sc)
369 {
370 uint32_t val;
371
372 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST);
373 val |= MACRO_RST;
374 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val);
375 delay(10);
376 val &= ~MACRO_RST;
377 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PHY_TEST, val);
378 }
379
380 int
anxdp_link_configure(struct anxdp_softc * sc)381 anxdp_link_configure(struct anxdp_softc *sc)
382 {
383 uint8_t values[2];
384 int error;
385
386 values[0] = drm_dp_link_rate_to_bw_code(sc->sc_link_rate);
387 values[1] = sc->sc_num_lanes;
388
389 if (sc->sc_dpcd[2] & DP_ENHANCED_FRAME_CAP)
390 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
391
392 error = drm_dp_dpcd_write(&sc->sc_dpaux, DP_LINK_BW_SET,
393 values, sizeof(values));
394 if (error < 0)
395 return error;
396
397 return 0;
398 }
399
400 int
anxdp_link_power_up(struct anxdp_softc * sc)401 anxdp_link_power_up(struct anxdp_softc *sc)
402 {
403 uint8_t value;
404 int error;
405
406 if (sc->sc_dpcd[0] < 0x11)
407 return 0;
408
409 error = drm_dp_dpcd_readb(&sc->sc_dpaux, DP_SET_POWER, &value);
410 if (error < 0)
411 return error;
412
413 value &= ~DP_SET_POWER_MASK;
414 value |= DP_SET_POWER_D0;
415
416 error = drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_SET_POWER, value);
417 if (error < 0)
418 return error;
419
420 delay(1000);
421 return 0;
422 }
423
424 void
anxdp_link_start(struct anxdp_softc * sc)425 anxdp_link_start(struct anxdp_softc *sc)
426 {
427 uint8_t training[4];
428 uint32_t val;
429
430 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LINK_BW_SET,
431 drm_dp_link_rate_to_bw_code(sc->sc_link_rate));
432 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_LANE_COUNT_SET,
433 sc->sc_num_lanes);
434 if (anxdp_link_configure(sc))
435 return;
436
437 for (u_int i = 0; i < sc->sc_num_lanes; i++) {
438 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
439 ANXDP_LNx_LINK_TRAINING_CTL(i));
440 val &= ~(PRE_EMPHASIS_SET(3)|DRIVE_CURRENT_SET(3));
441 val |= PRE_EMPHASIS_SET(0);
442 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
443 ANXDP_LNx_LINK_TRAINING_CTL(i), val);
444 }
445
446 if (anxdp_await_pll_lock(sc) != 0) {
447 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname);
448 }
449
450 for (u_int i = 0; i < sc->sc_num_lanes; i++) {
451 training[i] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
452 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
453 }
454
455 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
456 sc->sc_num_lanes);
457 }
458
459 void
anxdp_process_clock_recovery(struct anxdp_softc * sc)460 anxdp_process_clock_recovery(struct anxdp_softc *sc)
461 {
462 u_int i, tries;
463 uint8_t link_status[DP_LINK_STATUS_SIZE];
464 uint8_t training[4];
465
466 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET,
467 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1);
468 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
469 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
470
471 tries = 0;
472 again:
473 if (tries++ >= 10) {
474 printf("%s: cr fail\n", sc->sc_dev.dv_xname);
475 return;
476 }
477 drm_dp_link_train_clock_recovery_delay(&sc->sc_dpaux, sc->sc_dpcd);
478 if (DP_LINK_STATUS_SIZE !=
479 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
480 return;
481 }
482 if (!drm_dp_clock_recovery_ok(link_status, sc->sc_num_lanes)) {
483 goto cr_fail;
484 }
485
486 return;
487
488 cr_fail:
489 for (i = 0; i < sc->sc_num_lanes; i++) {
490 uint8_t vs, pe;
491 vs = drm_dp_get_adjust_request_voltage(link_status, i);
492 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
493 training[i] = vs | pe;
494 }
495 for (i = 0; i < sc->sc_num_lanes; i++) {
496 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
497 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]);
498 }
499 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
500 sc->sc_num_lanes);
501 goto again;
502 }
503
504 void
anxdp_process_eq(struct anxdp_softc * sc)505 anxdp_process_eq(struct anxdp_softc *sc)
506 {
507 u_int i, tries;
508 uint8_t link_status[DP_LINK_STATUS_SIZE];
509 uint8_t training[4];
510
511 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET,
512 SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2);
513 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
514 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2);
515
516 tries = 0;
517 again:
518 if (tries++ >= 10) {
519 printf("%s: eq fail\n", sc->sc_dev.dv_xname);
520 return;
521 }
522 drm_dp_link_train_channel_eq_delay(&sc->sc_dpaux, sc->sc_dpcd);
523 if (DP_LINK_STATUS_SIZE !=
524 drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
525 return;
526 }
527 if (!drm_dp_channel_eq_ok(link_status, sc->sc_num_lanes)) {
528 goto eq_fail;
529 }
530
531 return;
532
533 eq_fail:
534 for (i = 0; i < sc->sc_num_lanes; i++) {
535 uint8_t vs, pe;
536 vs = drm_dp_get_adjust_request_voltage(link_status, i);
537 pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
538 training[i] = vs | pe;
539 }
540 for (i = 0; i < sc->sc_num_lanes; i++) {
541 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
542 ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]);
543 }
544 drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
545 sc->sc_num_lanes);
546 goto again;
547 }
548
549 void
anxdp_train_link(struct anxdp_softc * sc)550 anxdp_train_link(struct anxdp_softc *sc)
551 {
552 anxdp_macro_reset(sc);
553
554 if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux,
555 DP_DPCD_REV, sc->sc_dpcd, DP_RECEIVER_CAP_SIZE)) {
556 printf("%s: link probe failed\n", sc->sc_dev.dv_xname);
557 return;
558 }
559
560 sc->sc_link_rate = drm_dp_bw_code_to_link_rate(sc->sc_dpcd[1]);
561 sc->sc_num_lanes = sc->sc_dpcd[2] & DP_MAX_LANE_COUNT_MASK;
562
563 if (anxdp_link_power_up(sc))
564 return;
565
566 anxdp_link_start(sc);
567 anxdp_process_clock_recovery(sc);
568 anxdp_process_eq(sc);
569
570 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TRAINING_PTN_SET, 0);
571 drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
572 DP_TRAINING_PATTERN_DISABLE);
573 }
574
575 void
anxdp_bringup(struct anxdp_softc * sc)576 anxdp_bringup(struct anxdp_softc *sc)
577 {
578 uint32_t val;
579
580 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
581 val &= ~VIDEO_EN;
582 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
583
584 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
585 val &= ~VIDEO_MUTE;
586 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
587
588 val = SW_FUNC_EN_N;
589 if (isrockchip(sc)) {
590 val |= RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N;
591 } else {
592 val |= MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
593 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N;
594 }
595 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
596
597 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2,
598 SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N |
599 LS_CLK_DOMAIN_FUNC_EN_N);
600
601 delay(30);
602
603 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_M_AUD_GEN_FILTER_TH, 2);
604 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL, 0x101);
605
606 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_SW_RESET,
607 RESET_DP_TX);
608
609 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_1,
610 TX_TERMINAL_CTRL_50_OHM);
611 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_2,
612 SEL_24M | TX_DVDD_BIT_1_0625V);
613 if (isrockchip(sc)) {
614 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_1,
615 REF_CLK_24M);
616 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_2,
617 0x95);
618 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_3,
619 0x40);
620 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_4,
621 0x58);
622 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_REG_5,
623 0x22);
624 }
625 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_ANALOG_CTL_3,
626 DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO);
627 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_PLL_FILTER_CTL_1,
628 PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | TX_CUR1_2X | TX_CUR_16_MA);
629 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_TX_AMP_TUNING_CTL, 0);
630
631 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1);
632 val &= ~SW_FUNC_EN_N;
633 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
634
635 anxdp_analog_power_up_all(sc);
636
637 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_COMMON_INT_STA_1,
638 PLL_LOCK_CHG);
639
640 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL);
641 val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
642 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DEBUG_CTL, val);
643
644 if (anxdp_await_pll_lock(sc) != 0) {
645 printf("%s: PLL lock timeout\n", sc->sc_dev.dv_xname);
646 }
647
648 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2);
649 val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N |
650 AUX_FUNC_EN_N);
651 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_2, val);
652
653 anxdp_init_hpd(sc);
654 anxdp_init_aux(sc);
655 }
656
657 void
anxdp_bridge_enable(struct drm_bridge * bridge)658 anxdp_bridge_enable(struct drm_bridge *bridge)
659 {
660 struct anxdp_softc *sc = bridge->driver_private;
661 uint32_t val;
662
663 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1);
664 if (isrockchip(sc)) {
665 val &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
666 } else {
667 val &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
668 val |= MASTER_VID_FUNC_EN_N;
669 }
670 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_FUNC_EN_1, val);
671
672 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10);
673 val &= ~(SLAVE_I_SCAN_CFG|SLAVE_VSYNC_P_CFG|SLAVE_HSYNC_P_CFG);
674 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_INTERLACE) != 0)
675 val |= SLAVE_I_SCAN_CFG;
676 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NVSYNC) != 0)
677 val |= SLAVE_VSYNC_P_CFG;
678 if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NHSYNC) != 0)
679 val |= SLAVE_HSYNC_P_CFG;
680 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_10, val);
681
682 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_SOC_GENERAL_CTL,
683 AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE);
684
685 anxdp_train_link(sc);
686
687 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1);
688 val |= VIDEO_EN;
689 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_VIDEO_CTL_1, val);
690
691 if (sc->sc_panel != NULL &&
692 sc->sc_panel->funcs != NULL &&
693 sc->sc_panel->funcs->enable != NULL)
694 sc->sc_panel->funcs->enable(sc->sc_panel);
695 }
696
697 void
anxdp_bridge_pre_enable(struct drm_bridge * bridge)698 anxdp_bridge_pre_enable(struct drm_bridge *bridge)
699 {
700 }
701
702 void
anxdp_bridge_disable(struct drm_bridge * bridge)703 anxdp_bridge_disable(struct drm_bridge *bridge)
704 {
705 }
706
707 void
anxdp_bridge_post_disable(struct drm_bridge * bridge)708 anxdp_bridge_post_disable(struct drm_bridge *bridge)
709 {
710 }
711
712 void
anxdp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)713 anxdp_bridge_mode_set(struct drm_bridge *bridge,
714 const struct drm_display_mode *mode,
715 const struct drm_display_mode *adjusted_mode)
716 {
717 struct anxdp_softc *sc = bridge->driver_private;
718
719 sc->sc_curmode = *adjusted_mode;
720 }
721
722 bool
anxdp_bridge_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)723 anxdp_bridge_mode_fixup(struct drm_bridge *bridge,
724 const struct drm_display_mode *mode,
725 struct drm_display_mode *adjusted_mode)
726 {
727 return true;
728 }
729
730 const struct drm_bridge_funcs anxdp_bridge_funcs = {
731 .attach = anxdp_bridge_attach,
732 .enable = anxdp_bridge_enable,
733 .pre_enable = anxdp_bridge_pre_enable,
734 .disable = anxdp_bridge_disable,
735 .post_disable = anxdp_bridge_post_disable,
736 .mode_set = anxdp_bridge_mode_set,
737 .mode_fixup = anxdp_bridge_mode_fixup,
738 };
739
740 ssize_t
anxdp_dp_aux_transfer(struct drm_dp_aux * dpaux,struct drm_dp_aux_msg * dpmsg)741 anxdp_dp_aux_transfer(struct drm_dp_aux *dpaux, struct drm_dp_aux_msg *dpmsg)
742 {
743 struct anxdp_softc *sc = container_of(dpaux, struct anxdp_softc,
744 sc_dpaux);
745 size_t loop_timeout = 0;
746 uint32_t val;
747 size_t i;
748 ssize_t ret = 0;
749
750 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_BUFFER_DATA_CTL,
751 BUF_CLR);
752
753 val = AUX_LENGTH(dpmsg->size);
754 if ((dpmsg->request & DP_AUX_I2C_MOT) != 0)
755 val |= AUX_TX_COMM_MOT;
756
757 switch (dpmsg->request & ~DP_AUX_I2C_MOT) {
758 case DP_AUX_I2C_WRITE:
759 break;
760 case DP_AUX_I2C_READ:
761 val |= AUX_TX_COMM_READ;
762 break;
763 case DP_AUX_NATIVE_WRITE:
764 val |= AUX_TX_COMM_DP;
765 break;
766 case DP_AUX_NATIVE_READ:
767 val |= AUX_TX_COMM_READ | AUX_TX_COMM_DP;
768 break;
769 }
770
771 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_1, val);
772 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_7_0,
773 AUX_ADDR_7_0(dpmsg->address));
774 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_15_8,
775 AUX_ADDR_15_8(dpmsg->address));
776 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_ADDR_19_16,
777 AUX_ADDR_19_16(dpmsg->address));
778
779 if (!(dpmsg->request & DP_AUX_I2C_READ)) {
780 for (i = 0; i < dpmsg->size; i++) {
781 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
782 ANXDP_BUF_DATA(i),
783 ((const uint8_t *)(dpmsg->buffer))[i]);
784 ret++;
785 }
786 }
787
788
789 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2,
790 AUX_EN | ((dpmsg->size == 0) ? ADDR_ONLY : 0));
791
792 loop_timeout = 0;
793 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_CTL_2);
794 while ((val & AUX_EN) != 0) {
795 if (++loop_timeout > 20000) {
796 ret = -ETIMEDOUT;
797 goto out;
798 }
799 delay(25);
800 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
801 ANXDP_AUX_CH_CTL_2);
802 }
803
804 loop_timeout = 0;
805 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA);
806 while (!(val & RPLY_RECEIV)) {
807 if (++loop_timeout > 2000) {
808 ret = -ETIMEDOUT;
809 goto out;
810 }
811 delay(10);
812 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
813 ANXDP_DP_INT_STA);
814 }
815
816 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA,
817 RPLY_RECEIV);
818
819 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA);
820 if ((val & AUX_ERR) != 0) {
821 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ANXDP_DP_INT_STA,
822 AUX_ERR);
823 ret = -EREMOTEIO;
824 goto out;
825 }
826
827 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_CH_STA);
828 if (AUX_STATUS(val) != 0) {
829 ret = -EREMOTEIO;
830 goto out;
831 }
832
833 if ((dpmsg->request & DP_AUX_I2C_READ)) {
834 for (i = 0; i < dpmsg->size; i++) {
835 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
836 ANXDP_BUF_DATA(i));
837 ((uint8_t *)(dpmsg->buffer))[i] = val & 0xffU;
838 ret++;
839 }
840 }
841
842 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ANXDP_AUX_RX_COMM);
843 if (val == AUX_RX_COMM_AUX_DEFER)
844 dpmsg->reply = DP_AUX_NATIVE_REPLY_DEFER;
845 else if (val == AUX_RX_COMM_I2C_DEFER)
846 dpmsg->reply = DP_AUX_I2C_REPLY_DEFER;
847 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
848 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
849 dpmsg->reply = DP_AUX_I2C_REPLY_ACK;
850 else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
851 (dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
852 dpmsg->reply = DP_AUX_NATIVE_REPLY_ACK;
853
854 out:
855 if (ret < 0)
856 anxdp_init_aux(sc);
857
858 return ret;
859 }
860
861 void
anxdp_dpms(struct anxdp_softc * sc,int mode)862 anxdp_dpms(struct anxdp_softc *sc, int mode)
863 {
864 switch (mode) {
865 case DRM_MODE_DPMS_ON:
866 #ifdef notyet
867 pmf_event_inject(NULL, PMFE_DISPLAY_ON);
868 #endif
869 break;
870 case DRM_MODE_DPMS_STANDBY:
871 case DRM_MODE_DPMS_SUSPEND:
872 case DRM_MODE_DPMS_OFF:
873 #ifdef notyet
874 pmf_event_inject(NULL, PMFE_DISPLAY_OFF);
875 #endif
876 break;
877 }
878 }
879
880 int
anxdp_attach(struct anxdp_softc * sc)881 anxdp_attach(struct anxdp_softc *sc)
882 {
883 sc->sc_dpaux.name = "DP Aux";
884 sc->sc_dpaux.transfer = anxdp_dp_aux_transfer;
885 sc->sc_dpaux.dev = &sc->sc_dev;
886 if (drm_dp_aux_register(&sc->sc_dpaux) != 0) {
887 printf("%s: registering DP Aux failed\n", sc->sc_dev.dv_xname);
888 }
889
890 anxdp_bringup(sc);
891
892 return 0;
893 }
894
895 int
anxdp_bind(struct anxdp_softc * sc,struct drm_encoder * encoder)896 anxdp_bind(struct anxdp_softc *sc, struct drm_encoder *encoder)
897 {
898 int error;
899
900 sc->sc_bridge.driver_private = sc;
901 sc->sc_bridge.funcs = &anxdp_bridge_funcs;
902 sc->sc_bridge.encoder = encoder;
903
904 error = drm_bridge_attach(encoder, &sc->sc_bridge, NULL, 0);
905 if (error != 0)
906 return EIO;
907
908 if (sc->sc_panel != NULL && sc->sc_panel->funcs != NULL &&
909 sc->sc_panel->funcs->prepare != NULL)
910 sc->sc_panel->funcs->prepare(sc->sc_panel);
911
912 return 0;
913 }
914