1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #ifndef _IGA_TYPES_EXT_HPP 10 #define _IGA_TYPES_EXT_HPP 11 12 #include "iga_bxml_ops.hpp" 13 #include "iga_bxml_enums.hpp" 14 #include "iga_types_swsb.hpp" 15 16 namespace iga 17 { 18 enum class RegName 19 { 20 INVALID = 0, // ENCODING 21 ARF_NULL, // null 0000b 22 ARF_A, // a# 0001b 23 ARF_ACC, // acc# ... 0010b with RegNum[3:0] = 0..1 for acc0-acc1 24 // XE 0..3 for acc0-acc3 25 26 // Math Macro Exponent (or Extended). 27 // 28 // Holds a 2b part of the exponent for IEEE-accurate math sequences 29 // using madm and math.{invm,rsqrtm} 30 // Formerly known as acc2-acc9. Still encodes the same. 31 // sometimes called "Special Accumulators" 32 // formerly called acc2-acc9 used in madm and 33 ARF_MME, // mme# ... 0010b with RegNum[3:0] = 2..9 for mme0-mme7 34 // XE RegNum[3:0] = 8..15 for mme0-mme7 35 36 ARF_F, // f# 0011b 37 ARF_CE, // ce 0100b 38 ARF_MSG, // msg# 0101b 39 ARF_SP, // sp 0110b 40 ARF_SR, // sr# 0111b 41 ARF_CR, // cr# 1000b 42 ARF_N, // n# 1001b 43 ARF_IP, // ip 1010b 44 ARF_TDR, // tdr 1011b 45 ARF_TM, // tm# 1100b 46 ARF_FC, // fc# 1101b 47 // ... reserved 48 ARF_DBG, // dbg0 1111b 49 GRF_R, // GRF N/A 50 }; 51 52 enum class Type 53 { 54 INVALID, 55 56 // sub-byte types for dpas 57 U1, U2, U4, 58 S2, S4, 59 // for S8 and U8 use B and UB 60 UB, 61 B, 62 UW, 63 W, 64 UD, 65 D, 66 UQ, 67 Q, 68 69 HF, 70 QF, 71 BF, 72 HF8, 73 BF8, 74 TF32, 75 76 F, 77 DF, 78 NF, 79 80 V, 81 UV, 82 VF, 83 }; 84 85 // an operand type 86 enum class Kind { 87 INVALID, // an invalid or uninitialized operand 88 DIRECT, // direct register reference 89 MACRO, // madm or math.invm or math.rsqrtm 90 INDIRECT, // register-indriect access 91 IMMEDIATE, // immediate value 92 LABEL, // block target (can be numeric label/i.e. imm value) 93 }; 94 95 enum class SFMessageType 96 { 97 INVALID = -1, 98 99 MSD0R_HWB, 100 MSD0W_HWB, 101 MT0R_OWB, 102 MT0R_OWUB, 103 MT0R_OWDB, 104 MT0R_DWS, 105 MT0R_BS, 106 MT0_MEMFENCE, 107 MT0W_OWB, 108 MT0W_OWDB, 109 MT0W_DWS, 110 MT0W_BS, 111 MT1R_T, 112 MT1R_US, 113 MT1A_UI, 114 MT1A_UI4x2, 115 MT1R_MB, 116 MT1R_TS, 117 MT1A_TA, 118 MT1A_TA4x2, 119 MT1W_US, 120 MT1W_MB, 121 MT1A_TC, 122 MT1A_TC4x2, 123 MT1W_TS, 124 MT1R_A64_SB, 125 MT1R_A64_US, 126 MT1A_A64_UI, 127 MT1A_A64_UI4x2, 128 MT1R_A64_B, 129 MT1W_A64_B, 130 MT1W_A64_US, 131 MT1W_A64_SB, 132 MT2R_US, 133 MT2R_A64_SB, 134 MT2R_A64_US, 135 MT2R_BS, 136 MT2W_US, 137 MT2W_A64_US, 138 MT2W_A64_SB, 139 MT2W_BS, 140 MT_CC_OWB, 141 MT_CC_OWUB, 142 MT_CC_OWDB, 143 MT_CC_DWS, 144 MT_SC_OWUB, 145 MT_SC_MB, 146 MT_RSI, 147 MT_RTW, 148 MT_RTR, 149 MTR_MB, 150 MTRR_TS, 151 MTRA_TA, 152 MT_MEMFENCE, 153 MTW_MB, 154 MTRW_TS, 155 MT0R_US, 156 MT0A_UI, 157 MT0W_US, 158 MT1A_UF4x2, 159 MT1A_UF, 160 MT1A_A64_UF, 161 MT1A_A64_UF4x2, 162 }; 163 164 enum class ExecSize 165 { 166 INVALID = 0, 167 168 SIMD1 = 1, 169 SIMD2 = 2, 170 SIMD4 = 4, 171 SIMD8 = 8, 172 SIMD16 = 16, 173 SIMD32 = 32, 174 }; 175 176 enum class ChannelOffset 177 { 178 M0, 179 M4, 180 M8, 181 M12, 182 M16, 183 M20, 184 M24, 185 M28, 186 }; 187 188 enum class MaskCtrl 189 { 190 NORMAL, 191 NOMASK, 192 }; 193 194 enum class FlagModifier 195 { 196 NONE = 0, // no flag modification 197 EQ, // equal (zero) 198 NE, // not-equal (not-zer) 199 GT, // greater than 200 GE, // greater than or equal 201 LT, // less than 202 LE, // less than or equal 203 // Reserved <= 7 204 OV = 8, // overflow 205 UN, // unordered (NaN) 206 EO = 0xFF, // special implicit flag modifier for math macros 207 // math.invm and math.rsqrtm. 208 // "The .eo means early out. It doesn't have bits in the 209 // instruction due to overlap with MathFC. The flag is set 210 // for early out conditions including division by 211 // 0, infinity, etc" 212 }; 213 214 enum class SrcModifier 215 { 216 NONE, 217 ABS, 218 NEG, 219 NEG_ABS, 220 }; 221 222 enum class DstModifier 223 { 224 NONE, 225 SAT, 226 }; 227 228 enum class PredCtrl 229 { 230 NONE, // predication is off 231 SEQ, // no explicit function; e.g. f0.0 232 ANYV, // .anyv; e.g. "f0.0.anyv". any from f0.0-f1.0 on the same channel // (<XeHPC) 233 ALLV, // all from f0.0-f1.0 on the same channel // (<XeHPC) 234 ANY2H, // (<XeHPC) 235 ALL2H, // (<XeHPC) 236 ANY4H, // (<XeHPC) 237 ALL4H, // (<XeHPC) 238 ANY8H, // (<XeHPC) 239 ALL8H, // (<XeHPC) 240 ANY16H, // (<XeHPC) 241 ALL16H, // (<XeHPC) 242 ANY32H, // (<XeHPC) 243 ALL32H, // (<XeHPC) 244 ANY, // any in execsize channels (>=XeHPC) 245 ALL, // all in execsize channels (>=XeHPC) 246 }; 247 248 // instruction options 249 enum class InstOpt { 250 ACCWREN, 251 ATOMIC, 252 BREAKPOINT, 253 COMPACTED, 254 EOT, 255 NOCOMPACT, 256 NODDCHK, 257 NODDCLR, 258 NOPREEMPT, 259 NOSRCDEPSET, 260 SWITCH, 261 SERIALIZE, 262 EXBSO, // XE_HP extended bindless surface offset 263 // implies CPS and Src1.Length come from EU encoding, not 264 CPS, // XE_HP coarse pixel shading 265 }; 266 } // namespace iga 267 #endif 268