1 /* 2 * Copyright (C) 2005 by Dominic Rath 3 * Dominic.Rath@gmx.de 4 * 5 * Copyright (C) 2006 by Magnus Lundin 6 * lundin@mlu.mine.nu 7 * 8 * Copyright (C) 2008 by Spencer Oliver 9 * spen@spen-soft.co.uk 10 * 11 * Copyright (C) 2009 by Øyvind Harboe 12 * oyvind.harboe@zylin.com 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #ifndef OPENOCD_TARGET_ARM_OPCODES_H 29 #define OPENOCD_TARGET_ARM_OPCODES_H 30 31 /** 32 * @file 33 * Macros used to generate various ARM or Thumb opcodes. 34 */ 35 36 /* ARM mode instructions */ 37 38 /* Store multiple increment after 39 * Rn: base register 40 * List: for each bit in list: store register 41 * S: in privileged mode: store user-mode registers 42 * W = 1: update the base register. W = 0: leave the base register untouched 43 */ 44 #define ARMV4_5_STMIA(Rn, List, S, W) \ 45 (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) 46 47 /* Load multiple increment after 48 * Rn: base register 49 * List: for each bit in list: store register 50 * S: in privileged mode: store user-mode registers 51 * W = 1: update the base register. W = 0: leave the base register untouched 52 */ 53 #define ARMV4_5_LDMIA(Rn, List, S, W) \ 54 (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) 55 56 /* MOV r8, r8 */ 57 #define ARMV4_5_NOP (0xe1a08008) 58 59 /* Move PSR to general purpose register 60 * R = 1: SPSR R = 0: CPSR 61 * Rn: target register 62 */ 63 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) 64 65 /* Store register 66 * Rd: register to store 67 * Rn: base register 68 */ 69 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) 70 71 /* Load register 72 * Rd: register to load 73 * Rn: base register 74 */ 75 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) 76 77 /* Move general purpose register to PSR 78 * R = 1: SPSR R = 0: CPSR 79 * Field: Field mask 80 * 1: control field 2: extension field 4: status field 8: flags field 81 * Rm: source register 82 */ 83 #define ARMV4_5_MSR_GP(Rm, Field, R) \ 84 (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) 85 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ 86 (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) 87 88 /* Load Register Word Immediate Post-Index 89 * Rd: register to load 90 * Rn: base register 91 */ 92 #define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) 93 94 /* Load Register Halfword Immediate Post-Index 95 * Rd: register to load 96 * Rn: base register 97 */ 98 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) 99 100 /* Load Register Byte Immediate Post-Index 101 * Rd: register to load 102 * Rn: base register 103 */ 104 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) 105 106 /* Store register Word Immediate Post-Index 107 * Rd: register to store 108 * Rn: base register 109 */ 110 #define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) 111 112 /* Store register Halfword Immediate Post-Index 113 * Rd: register to store 114 * Rn: base register 115 */ 116 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) 117 118 /* Store register Byte Immediate Post-Index 119 * Rd: register to store 120 * Rn: base register 121 */ 122 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) 123 124 /* Branch (and Link) 125 * Im: Branch target (left-shifted by 2 bits, added to PC) 126 * L: 1: branch and link 0: branch only 127 */ 128 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) 129 130 /* Branch and exchange (ARM state) 131 * Rm: register holding branch target address 132 */ 133 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) 134 135 /* Copies two words from two ARM core registers 136 * into a doubleword extension register, or 137 * from a doubleword extension register to two ARM core registers. 138 * See Armv7-A arch reference manual section A8.8.345 139 * Rt: Arm core register 1 140 * Rt2: Arm core register 2 141 * Vm: The doubleword extension register 142 * M: m = UInt(M:Vm); 143 * op: to_arm_registers = (op == ‘1’); 144 */ 145 #define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \ 146 (0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \ 147 ((Rt) << 12) | ((M) << 5) | (Vm)) 148 149 /* Moves the value of the FPSCR to an ARM core register 150 * Rt: Arm core register 151 */ 152 #define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12)) 153 154 /* Moves the value of an ARM core register to the FPSCR. 155 * Rt: Arm core register 156 */ 157 #define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12)) 158 159 /* Store data from coprocessor to consecutive memory 160 * See Armv7-A arch doc section A8.6.187 161 * P: 1=index mode (offset from Rn) 162 * U: 1=add, 0=subtract Rn address with imm 163 * D: Opcode D encoding 164 * W: write back the offset start address to the Rn register 165 * CP: Coprocessor number (4 bits) 166 * CRd: Coprocessor source register (4 bits) 167 * Rn: Base register for memory address (4 bits) 168 * imm: Immediate value (0 - 1020, must be divisible by 4) 169 */ 170 #define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \ 171 (0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ 172 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2)) 173 174 /* Loads data from consecutive memory to coprocessor 175 * See Armv7-A arch doc section A8.6.51 176 * P: 1=index mode (offset from Rn) 177 * U: 1=add, 0=subtract Rn address with imm 178 * D: Opcode D encoding 179 * W: write back the offset start address to the Rn register 180 * CP: Coprocessor number (4 bits) 181 * CRd: Coprocessor dest register (4 bits) 182 * Rn: Base register for memory address (4 bits) 183 * imm: Immediate value (0 - 1020, must be divisible by 4) 184 */ 185 #define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \ 186 (0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ 187 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2)) 188 189 /* Move to ARM register from coprocessor 190 * CP: Coprocessor number 191 * op1: Coprocessor opcode 192 * Rd: destination register 193 * CRn: first coprocessor operand 194 * CRm: second coprocessor operand 195 * op2: Second coprocessor opcode 196 */ 197 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \ 198 (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ 199 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 200 201 /* Move to coprocessor from ARM register 202 * CP: Coprocessor number 203 * op1: Coprocessor opcode 204 * Rd: destination register 205 * CRn: first coprocessor operand 206 * CRm: second coprocessor operand 207 * op2: Second coprocessor opcode 208 */ 209 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \ 210 (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ 211 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 212 213 /* Breakpoint instruction (ARMv5) 214 * Im: 16-bit immediate 215 */ 216 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 4) | (Im & 0xf)) 217 218 219 /* Thumb mode instructions 220 * 221 * NOTE: these 16-bit opcodes fill both halves of a word with the same 222 * value. The reason for this is that when we need to execute Thumb 223 * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry), 224 * we must shift 32 bits to the bus using scan chain 1 ... if we write 225 * both halves, we don't need to track which half matters. On ARMv6 and 226 * ARMv7 we don't execute Thumb instructions in debug mode; the ITR 227 * register does not accept Thumb (or Thumb2) opcodes. 228 */ 229 230 /* Store register (Thumb mode) 231 * Rd: source register 232 * Rn: base register 233 */ 234 #define ARMV4_5_T_STR(Rd, Rn) \ 235 ((0x6000 | (Rd) | ((Rn) << 3)) | \ 236 ((0x6000 | (Rd) | ((Rn) << 3)) << 16)) 237 238 /* Load register (Thumb state) 239 * Rd: destination register 240 * Rn: base register 241 */ 242 #define ARMV4_5_T_LDR(Rd, Rn) \ 243 ((0x6800 | ((Rn) << 3) | (Rd)) \ 244 | ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) 245 246 /* Load multiple (Thumb state) 247 * Rn: base register 248 * List: for each bit in list: store register 249 */ 250 #define ARMV4_5_T_LDMIA(Rn, List) \ 251 ((0xc800 | ((Rn) << 8) | (List)) \ 252 | ((0xc800 | ((Rn) << 8) | (List)) << 16)) 253 254 /* Load register with PC relative addressing 255 * Rd: register to load 256 */ 257 #define ARMV4_5_T_LDR_PCREL(Rd) \ 258 ((0x4800 | ((Rd) << 8)) \ 259 | ((0x4800 | ((Rd) << 8)) << 16)) 260 261 /* Move hi register (Thumb mode) 262 * Rd: destination register 263 * Rm: source register 264 */ 265 #define ARMV4_5_T_MOV(Rd, Rm) \ 266 ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ 267 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \ 268 | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ 269 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) 270 271 /* No operation (Thumb mode) 272 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two 273 * architected NOPs, 16-bit and 32-bit. 274 */ 275 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) 276 277 /* Move immediate to register (Thumb state) 278 * Rd: destination register 279 * Im: 8-bit immediate value 280 */ 281 #define ARMV4_5_T_MOV_IM(Rd, Im) \ 282 ((0x2000 | ((Rd) << 8) | (Im)) \ 283 | ((0x2000 | ((Rd) << 8) | (Im)) << 16)) 284 285 /* Branch and Exchange 286 * Rm: register containing branch target 287 */ 288 #define ARMV4_5_T_BX(Rm) \ 289 ((0x4700 | ((Rm) << 3)) \ 290 | ((0x4700 | ((Rm) << 3)) << 16)) 291 292 /* Branch (Thumb state) 293 * Imm: Branch target 294 */ 295 #define ARMV4_5_T_B(Imm) \ 296 ((0xe000 | (Imm)) \ 297 | ((0xe000 | (Imm)) << 16)) 298 299 /* Breakpoint instruction (ARMv5) (Thumb state) 300 * Im: 8-bit immediate 301 */ 302 #define ARMV5_T_BKPT(Im) \ 303 ((0xbe00 | (Im)) \ 304 | ((0xbe00 | (Im)) << 16)) 305 306 /* Move to Register from Special Register 307 * 32 bit Thumb2 instruction 308 * Rd: destination register 309 * SYSm: source special register 310 */ 311 #define ARM_T2_MRS(Rd, SYSm) \ 312 ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) 313 314 /* Move from Register from Special Register 315 * 32 bit Thumb2 instruction 316 * Rd: source register 317 * SYSm: destination special register 318 */ 319 #define ARM_T2_MSR(SYSm, Rn) \ 320 ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) 321 322 /* Change Processor State. 323 * 16 bit Thumb2 instruction 324 * Rd: source register 325 * IF: A_FLAG and/or I_FLAG and/or F_FLAG 326 */ 327 #define A_FLAG 4 328 #define I_FLAG 2 329 #define F_FLAG 1 330 #define ARM_T2_CPSID(IF) \ 331 ((0xB660 | (1 << 8) | ((IF)&0x3)) \ 332 | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16)) 333 #define ARM_T2_CPSIE(IF) \ 334 ((0xB660 | (0 << 8) | ((IF)&0x3)) \ 335 | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16)) 336 337 #endif /* OPENOCD_TARGET_ARM_OPCODES_H */ 338