1 // author: esteve <youterm.com> 2 #ifndef ARM_H 3 #define ARM_H 4 5 #define ARM_SIZEOF_INST 4 6 7 #define ARM_COND_EQ 0x00000000 // Z set, equal 8 #define ARM_COND_NE 0x10000000 // Z clear, no equal 9 #define ARM_COND_HS 0x20000000 // C set, unsigned higher or same 10 #define ARM_COND_LO 0x30000000 // C clear, unsgined lower 11 #define ARM_COND_MI 0x40000000 // N set , negative 12 #define ARM_COND_PL 0x50000000 // N clear , positive or zero 13 #define ARM_COND_VS 0x60000000 // V set , overflow 14 #define ARM_COND_VC 0x70000000 // V clear, no overflow 15 #define ARM_COND_HI 0x80000000 // C set and Z clear, unsigned higher 16 #define ARM_COND_LS 0x90000000 // C clear or Z, unsigned lower or same 17 #define ARM_COND_GE 0xa0000000 // N set and V set , or N clear V clear, >= 18 #define ARM_COND_LT 0xb0000000 // N clear and V clear , or N clear V set, < 19 #define ARM_COND_GT 0xc0000000 // > 20 #define ARM_COND_LE 0xd0000000 // <= 21 #define ARM_COND_AL 0xe0000000 // Always 22 #define ARM_COND_NV 0xf0000000 // reserved 23 #define ARM_COND_MASK 0xf0000000 24 25 // registers ( TODO ) 26 #define ARM_R0 0 27 #define ARM_R1 1 28 #define ARM_R2 2 29 #define ARM_R3 3 30 #define ARM_R4 4 31 #define ARM_R5 5 32 #define ARM_R6 6 33 #define ARM_R7 7 34 #define ARM_R8 8 35 #define ARM_R9 9 36 #define ARM_R10 10 37 #define ARM_R11 11 38 #define ARM_R12 12 39 #define ARM_R13 13 40 #define ARM_R14 14 41 #define ARM_R15 15 42 #define ARM_PC ARM_R15 43 #define ARM_LR ARM_R14 44 #define ARM_SP ARM_R13 45 #define ARM_FP ARM_R11 46 47 // branch instruction 48 #define ARM_BRANCH_I 0x0a000000 49 #define ARM_BRANCH_I_MASK 0x0E000000 50 #define ARM_BRANCH_LINK 0x01000000 51 #define ARM_BRANCH_NOLINK 0x00000000 52 53 // data processing DP instruction 54 #define ARM_DP_I 0x00 55 /* 56 0000 = AND - Rd:= Op1 AND Op2 57 0010 = SUB - Rd:= Op1 - Op2 58 0011 = RSB - Rd:= Op2 - Op1 59 0100 = ADD - Rd:= Op1 + Op2 60 0101 = ADC - Rd:= Op1 + Op2 + C 61 0110 = SBC - Rd:= Op1 - Op2 + C 62 0111 = RSC - Rd:= Op2 - Op1 + C 63 1000 = TST - set condition codes on Op1 AND Op2 64 1001 = TEQ - set condition codes on Op1 EOR Op2 65 1010 = CMP - set condition codes on Op1 - Op2 66 1011 = CMN - set condition codes on Op1 + Op2 67 1100 = ORR - Rd:= Op1 OR Op2 68 1101 = MOV - Rd:= Op2 69 1110 = BIC - Rd:= Op1 AND NOT Op2 70 1111 = MVN - Rd:= NOT Op2 */ 71 72 73 74 #define ARM_DP_AND 0x0 75 #define ARM_DP_EOR (0x01<<21) 76 #define ARM_DP_SUB (0x02<<21) 77 #define ARM_DP_RSB (0x03<<21) 78 #define ARM_DP_ADD (0x04<<21) 79 #define ARM_DP_ADC (0x05<<21) 80 #define ARM_DP_SBC (0x06<<21) 81 #define ARM_DP_RSC (0x07<<21) 82 #define ARM_DP_TST (0x08<<21) 83 #define ARM_DP_TEQ (0x09<<21) 84 #define ARM_DP_CMP (0x0a<<21) 85 #define ARM_DP_CMN (0x0b<<21) 86 #define ARM_DP_ORR (0x0c<<21) 87 #define ARM_DP_MOV (0x0d<<21) 88 #define ARM_DP_BIC (0x0e<<21) 89 #define ARM_DP_MVN (0x0f<<21) 90 91 // TODO: register shift 92 93 #define ARM_DP_IMM 0x2000000 94 #define ARM_DP_NOIMM 0x000000 95 96 #define ARM_DP_SETCOND (1<<20) 97 #define ARM_DP_NOSETCOND 0 98 99 100 // arm data transfer instruction dtx 101 #define ARM_DTX_I 0x04000000 102 #define ARM_DTX_I_MASK 0x0C000000 103 104 //is immediate value 105 #define ARM_DTX_IM 0x00 106 #define ARM_DTX_NOTIM (0x01<<25) 107 // pre / post indexing 108 #define ARM_DTX_PRE (0x01<<24) 109 #define ARM_DTX_POST 0x00 110 // up / down ( add /substract ) 111 #define ARM_DTX_ADD (0x01<<23) 112 #define ARM_DTX_SUB 0x00 113 // byte word operation 114 #define ARM_DTX_BYTE (0x01<<22) 115 #define ARM_DTX_WORD 0x00 116 // write back 117 #define ARM_DTX_NOWB 0x00 118 #define ARM_DTX_WB (0x01<<21) 119 // load store 120 #define ARM_DTX_LOAD (0x01<<20) 121 #define ARM_DTX_STORE 0x00 122 123 // mascara registre desti 124 #define ARM_DTX_RD_MASK ( 0x0F << 12 ) 125 126 127 // arm block data transfer instruction dtm 128 #define ARM_DTM_I 0x08000000 129 #define ARM_DTM_I_MASK 0x0E000000 130 131 // pre / post indexing 132 #define ARM_DTM_PRE (0x01<<24) 133 #define ARM_DTM_POST 0x00 134 135 // up / down ( add /substract ) 136 #define ARM_DTM_ADD (0x01<<23) 137 #define ARM_DTM_SUB 0x00 138 139 // write back 140 #define ARM_DTM_NOWB 0x00 141 #define ARM_DTM_WB (0x01<<21) 142 143 // load store 144 #define ARM_DTM_LOAD (0x01<<20) 145 #define ARM_DTM_STORE 0x00 146 147 typedef struct _arm_label { 148 char name[100]; 149 unsigned int at; 150 } arm_label; 151 152 typedef struct _arm_code_seq { 153 unsigned int base; 154 unsigned int max_ins; 155 unsigned int act_ins; 156 157 int * codeseq; 158 arm_label *def_labels; 159 unsigned int lastlabel; 160 } arm_code_seq; 161 162 #endif 163